专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20060234497A1 Interconnect structure and method of fabrication of same 失效
公开(公告)号：US20060234497A1
公开(公告)日：2006-10-19
申请号：US11107074
申请日：2005-04-15
申请人： Chih-Chao Yang , Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Meeyoung Yoon
发明人： Chih-Chao Yang , Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Meeyoung Yoon
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.

62. 发明申请

US20060183308A1 Method of etching dual pre-doped polysilicon gate stacks using carbon-containing gases additions 失效
标题翻译：使用含碳气体添加剂蚀刻双预掺杂多晶硅栅极叠层的方法
公开(公告)号：US20060183308A1
公开(公告)日：2006-08-17
申请号：US10730891
申请日：2003-12-10
申请人： Ying Zhang , Timothy Dalton , Wesley Natzle
发明人： Ying Zhang , Timothy Dalton , Wesley Natzle
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L21/28123 , H01L21/32137 , H01L21/32139
摘要： A method for making dual pre-doped gate stacks used in semiconductor applications such as complementary metal oxide semiconductor (CMOS) devices and metal oxide semiconductor field effect transistors (MOSFETs) is provided. The method involves providing at least one pre-doped conductive layer, such as poly silicon (poly-Si), on a gate stack and etching by exposing the conductive layer to an etching composition comprising at least one carbon containing gas. The carbon containing gas can be selected from gases having the general formula CxHy, such as, for example, CH4, C2H2, C2H4, and C2H6. The carbon containing gas can further be selected from gases having the general formula CxHyA, wherein a can represent one or more additional substituents selected from O, N, P, S, F, Cl, Br, and I. The processes can result in dual pre-doped gate stacks having essentially vertical sidewalls and further having a width of at least about 3 nm, such as from about 5 nm to about 150 nm.
摘要翻译：提供了在半导体应用中使用诸如互补金属氧化物半导体（CMOS）器件和金属氧化物半导体场效应晶体管（MOSFET）的双预预掺杂栅叠层的方法。该方法包括在栅叠层上提供至少一个预先掺杂的导电层，例如多晶硅（poly-Si），以及通过将导电层暴露于含有至少一种含碳气体的蚀刻组合物进行蚀刻。含碳气体可以选自具有通式C x H H y H的气体，例如CH 4，C 3， H 2 H 2，C 2 H 4，和C 2 H 2， 6 。含碳气体还可以选自具有通式C x H A A A的气体，其中a可以表示一个或多个选自O，N，P ，S，F，Cl，Br和I.该工艺可以导致具有基本上垂直的侧壁并且还具有至少约3nm，例如约5nm至约150nm的宽度的双预掺杂栅叠层。

63. 发明申请

US20060043435A1 Nano-scaled gate structure with self-interconnect capabilities 失效
公开(公告)号：US20060043435A1
公开(公告)日：2006-03-02
申请号：US10930989
申请日：2004-08-31
申请人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens , Keith Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens , Keith Wong , Chih-Chao Yang
IPC分类号： H01L29/76
CPC分类号： H01L21/28114 , H01L21/76895 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L27/0629 , H01L27/088 , H01L29/41783 , H01L29/6653 , H01L29/66545
摘要： Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically connects the gate conductor to a local diffusion region. Another semiconductor device comprises two gate conductors with enlarged upper portions which merge to create electrically interconnected gate conductors. Methods for forming the above semiconductor devices are also described and claimed.

64. 发明申请

US20050230831A1 Structure to improve adhesion between top CVD low-k dielectiric and dielectric capping layer 有权
标题翻译：结构以改善顶部CVD低k介电层和介电顶盖层之间的粘附
公开(公告)号：US20050230831A1
公开(公告)日：2005-10-20
申请号：US10827693
申请日：2004-04-19
申请人： Lawrence Clevenger , Stefanie Chiras , Timothy Dalton , James Demarest , Derren Dunn , Chester Dziobkowski , Philip Flaitz , Michael Lane , James Lloyd , Darryl Restaino , Thomas Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence Clevenger , Stefanie Chiras , Timothy Dalton , James Demarest , Derren Dunn , Chester Dziobkowski , Philip Flaitz , Michael Lane , James Lloyd , Darryl Restaino , Thomas Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L21/312 , H01L21/316 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/532
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

65. 发明授权

US08471306B2 Double-sided integrated circuit chips 失效
标题翻译：双面集成电路芯片
公开(公告)号：US08471306B2
公开(公告)日：2013-06-25
申请号：US13192608
申请日：2011-07-28
申请人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号： H01L29/80 , H01L29/04 , H01L31/036
CPC分类号： G06F17/5077 , H01L21/6835 , H01L21/76895 , H01L21/84 , H01L23/481 , H01L23/535 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L29/045 , H01L2221/6835 , H01L2221/68359 , H01L2221/68368 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2924/01019 , H01L2924/01029 , H01L2924/0132 , H01L2924/1305 , H01L2924/14 , H01L2924/19041 , H01L2924/01007 , H01L2924/01022 , H01L2924/00
摘要： A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译：双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。下晶片可以包括布线水平。下部晶片可以包括用于触点的着陆焊盘。与下晶片的硅层的接触可以被硅化。

66. 发明授权

US07863734B2 Dual-sided chip attached modules 有权
标题翻译：双面芯片连接模块
公开(公告)号：US07863734B2
公开(公告)日：2011-01-04
申请号：US12186655
申请日：2008-08-06
申请人： Kerry Bernstein , Timothy Dalton , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Mark David Jaffe , Christopher David Muzzy , Wolfgang Sauter , Edmund Sprogis , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Dalton , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Mark David Jaffe , Christopher David Muzzy , Wolfgang Sauter , Edmund Sprogis , Anthony Kendall Stamper
IPC分类号： H01L23/34 , H01L23/48
CPC分类号： H01L24/10 , H01L23/13 , H01L23/481 , H01L23/49833 , H01L23/5385 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L2224/13 , H01L2224/13099 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H05K1/145 , H05K3/222 , H05K2201/10674 , Y10T436/171538 , Y10T436/172307 , H01L2924/00014 , H01L2924/00
摘要： An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.
摘要翻译：一种电子装置和包装电子装置的方法。该装置包括：第一基板，第二基板和具有第一侧和相对的第二侧的集成电路芯片，在第一侧上的第一组芯片焊盘和在集成的第二侧上的第二组芯片焊盘电路芯片，第一组芯片焊盘的芯片焊盘物理和电连接到第一衬底上的对应衬底焊盘，并且第二组芯片焊盘的芯片焊盘物理和电连接到衬底的衬底焊盘。

67. 发明授权

US07657995B2 Method of fabricating a microelectromechanical system (MEMS) switch 失效
标题翻译：制造微机电系统（MEMS）开关的方法
公开(公告)号：US07657995B2
公开(公告)日：2010-02-09
申请号：US11776835
申请日：2007-07-12
申请人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
发明人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01H11/00 , H01H65/00
CPC分类号： H01H59/0009 , H01H1/20 , H01H2001/0084 , H01H2001/0089 , Y10T29/49105 , Y10T29/49128 , Y10T29/49155 , Y10T29/49204 , Y10T29/49208
摘要： A method of fabricating a MEMS switch that is fully integratable in a semiconductor fabrication line. The method consists of forming two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; forming upper and lower electrode pairs and upper and lower interconnect wiring lines connected and disconnected by the rigid movable conductive plate. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines.
摘要翻译：一种制造可在半导体制造生产线中完全集成的MEMS开关的方法。该方法包括形成两个柱，其每端终止于盖中; 刚性可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松散地连接到引导柱; 形成上下电极对以及由刚性可移动导电板连接和断开的上下互连布线。导电板向上移动，使两条上部互连线路短路。相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。

68. 发明申请

US20090312046A1 INTELLIGENT WIRELESS POWER CHARGING SYSTEM 有权
标题翻译：智能无线充电系统
公开(公告)号：US20090312046A1
公开(公告)日：2009-12-17
申请号：US12137185
申请日：2008-06-11
申请人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens
发明人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens
IPC分类号： H04B7/00 , H04M1/00
CPC分类号： H02J50/20 , H02J7/025 , H02J17/00
摘要： A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.
摘要翻译：一种用于无线网络设备智能电源管理的系统和方法。该系统通过无线电力充电方法提供可靠的无线通信，以及在无线设备中维持电池的电力容量的方法。电池通过嵌入在无线设备内部的射频收集单元进行充电。智能无线电力充电系统还包括耦合到AC电力线的至少两个电池和至少两个RF适配器装置。第一个适配器设置为数据通信，而第二个适配器用于传输电源。此外，当在活动模式期间使用第一电池时，对第二电池进行无线充电。

69. 发明申请

US20080093342A1 ETCHING APPARATUS FOR SEMICONDUTOR FABRICATION 审中-公开
标题翻译：用于半导体制造的蚀刻装置
公开(公告)号：US20080093342A1
公开(公告)日：2008-04-24
申请号：US11962271
申请日：2007-12-21
申请人： Timothy Dalton , Emily Gallagher , Louis Kindt , Carey Thiel , Andrew Watts
发明人： Timothy Dalton , Emily Gallagher , Louis Kindt , Carey Thiel , Andrew Watts
IPC分类号： C23F1/00
CPC分类号： H01J37/32706 , H01J37/32091 , H01J37/32541
摘要： Method of operating an apparatus which allows etching different substrate etch areas of a substrate having different pattern densities at essentially the same etch rate. The apparatus includes (a) a chamber; (b) an anode and a cathode in the chamber; and (c) a bias power system coupled to the cathode, wherein the cathode includes multiple cathode segments. The operation method is as follows. A substrate to be etched is placed between the anode and cathode, wherein the substrate includes N substrate etch areas, and the N substrate etch areas are directly above the N cathode segments. N bias powers are determined which when being applied to the N cathode segments during an etching of the substrate, will result in essentially a same etch rate for the N substrate etch areas. Then, the bias power system is used to apply the N bias powers the N cathode segments.
摘要翻译：操作能够以基本上相同的蚀刻速率蚀刻具有不同图案密度的衬底的不同衬底蚀刻区域的装置的方法。该装置包括（a）室; （b）室中的阳极和阴极; 和（c）耦合到所述阴极的偏置功率系统，其中所述阴极包括多个阴极段。操作方法如下。要蚀刻的衬底放置在阳极和阴极之间，其中衬底包括N个衬底蚀刻区域，并且N个衬底蚀刻区域直接在N个阴极段上方。确定N偏置功率，当在衬底的蚀刻期间施加到N个阴极段时，将产生对于N个衬底蚀刻区域基本上相同的蚀刻速率。然后，使用偏置功率系统对N个阴极段施加N个偏置功率。

70. 发明授权

US07348870B2 Structure and method of fabricating a hinge type MEMS switch 有权
标题翻译：制造铰链式MEMS开关的结构和方法
公开(公告)号：US07348870B2
公开(公告)日：2008-03-25
申请号：US10905449
申请日：2005-01-05
申请人： Louis C. Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
发明人： Louis C. Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01H51/22
CPC分类号： H01H59/0009 , H01H1/20 , H01H2001/0084 , H01H2001/0089 , Y10T29/49105 , Y10T29/49128 , Y10T29/49155 , Y10T29/49204 , Y10T29/49208
摘要： A hinge type MEMS switch that is fully integratable within a semiconductor fabrication process, such as a CMOS, is described. The MEMS switch constructed on a substrate consists of two posts, each end thereof terminating in a cap; a movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; an upper and lower electrode pairs; and upper and lower interconnect wiring lines connected and disconnected by the movable conductive plate. When in the energized state, a low voltage level is applied to the upper electrode pair, while the lower electrode pair is grounded. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines. The MEMS switch thus formed generates an even force that provides the conductive plate with a translational movement, with the displacement being guided by the two vertical posts.
摘要翻译：描述了在诸如CMOS之类的半导体制造工艺中可完全集成的铰链式MEMS开关。构造在基板上的MEMS开关由两个柱构成，每个端部终止于盖; 可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松动地连接到引导柱; 上下电极对; 以及由可动导电板连接和断开的上下互连布线。当处于通电状态时，低电压电平施加到上电极对，而下电极对接地。导电板向上移动，使两条上部互连线路短路。相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。由此形成的MEMS开关产生均匀的力，其为导电板提供平移运动，位移由两个垂直柱引导。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式