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61. 发明授权

US08036775B2 Obstacle avoidance system for a user guided mobile robot 有权
标题翻译：用于导向移动机器人的障碍物回避系统
公开(公告)号：US08036775B2
公开(公告)日：2011-10-11
申请号：US11396643
申请日：2006-04-04
申请人： Kosei Matsumoto , Toshio Moriya , Kazuo Yano
发明人： Kosei Matsumoto , Toshio Moriya , Kazuo Yano
IPC分类号： G05D1/02 , G05D1/12 , G05D1/00 , G06F19/00
CPC分类号： G06N3/008 , G05D1/024 , G05D1/0242 , G05D1/0255 , G05D1/0274 , G05D2201/0211
摘要： The system includes a mobile apparatus that moves after receiving an input of a path. The system has a path-setting unit for setting the path of a mobile apparatus according to the inputted path, a measuring unit for measuring an environment in which the mobile apparatus exists, an extracting unit for extracting an object existence region in the environment according to the values measured by the measuring unit, a judging unit that judges the validity of the path according to (1) the path set by the path setting unit and (2) the object existence region extracted by the extracting unit, a position determining unit that determines a target position to which the mobile apparatus is to move by selecting it from the portions of the path judged as valid, and a movement controller for controlling the mobile apparatus to move to the target position.
摘要翻译：该系统包括在接收到路径的输入之后移动的移动装置。该系统具有路径设定单元，用于根据输入路径设定移动装置的路径，测量单元，用于测量移动装置存在的环境;提取单元，用于根据所述环境中的对象存在区域提取根据由测量单元测量的值，根据（1）由路径设置单元设置的路径和（2）由提取单元提取的对象存在区域来判断路径的有效性的判断单元，位置确定单元，通过从被判定为有效的路径的部分中选择移动装置来移动的目标位置，以及移动控制器，用于控制移动装置移动到目标位置。

62. 发明授权

US07294880B2 Semiconductor non-volatile memory cell with a plurality of charge storage regions 有权
标题翻译：具有多个电荷存储区域的半导体非易失性存储单元
公开(公告)号：US07294880B2
公开(公告)日：2007-11-13
申请号：US10919471
申请日：2004-08-17
申请人： Taro Osabe , Tomoyuki Ishii , Kazuo Yano , Takashi Kobayashi
发明人： Taro Osabe , Tomoyuki Ishii , Kazuo Yano , Takashi Kobayashi
IPC分类号： H01L27/108
CPC分类号： H01L27/11521 , B82Y10/00 , G11C16/0433 , G11C16/0458 , G11C16/0483 , G11C16/0491 , G11C16/10 , G11C16/26 , G11C2216/06 , H01L27/115 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.
摘要翻译：为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过细胞水平。

63. 发明授权

US07129741B2 Semiconductor integrated circuit device, storage medium on which cell library is stored and designing method for semiconductor integrated circuit 有权
标题翻译：半导体集成电路器件，其上存储有单元库的存储介质和用于半导体集成电路的设计方法
公开(公告)号：US07129741B2
公开(公告)日：2006-10-31
申请号：US10827291
申请日：2004-04-20
申请人： Naoki Katoh , Kazuo Yano , Yohei Akita , Mitsuru Hiraki
发明人： Naoki Katoh , Kazuo Yano , Yohei Akita , Mitsuru Hiraki
IPC分类号： H03K19/23
CPC分类号： H03K19/1731 , G06F17/505 , H03K19/0013
摘要： This invention provides a storage medium on which there is stored a cell library to design a semiconductor integrated circuit to satisfy low power consumption and high speed operation and a design method using the cell library. The cell library is registered with at least two kinds of cells which are different in delay and power consumption while having the same function and the same shape. To satisfy the specification of the semiconductor integrated circuit, one cell is selected from at least two kinds of cells of the cell library.
摘要翻译：本发明提供了一种存储介质，其上存储有一个单元库以设计半导体集成电路以满足低功耗和高速操作，以及使用该单元库的设计方法。细胞库与具有相同功能和相同形状的延迟和功耗不同的至少两种细胞登记。为了满足半导体集成电路的规格，从单元库的至少两种单元中选择一个单元。

64. 发明申请

US20060019695A1 Method of communication and base station 有权
标题翻译：通信方式和基站
公开(公告)号：US20060019695A1
公开(公告)日：2006-01-26
申请号：US10929793
申请日：2004-08-31
申请人： Masayuki Miyazaki , Minoru Oogushi , Kazuo Yano
发明人： Masayuki Miyazaki , Minoru Oogushi , Kazuo Yano
IPC分类号： H04B7/00 , H04B1/38 , H01Q11/12
CPC分类号： H04W52/287 , H04W52/0235 , Y02D70/142
摘要： There are provided a method of communication which can reliably transmit information from a base station to a wireless terminal in a system which can reduce power consumption by intermittent operation in which the wireless terminal repeats operating state and suspended state by power on and off and the base station used for the method. The method includes the steps of storing base station information such as a command or data supplied to the wireless terminal in the base station, transferring the wireless terminal from the suspended state to the operating state to transmit information from the sensor to the base station, coupling the base station information stored in the base station to a response signal to transmit it to the wireless terminal in the operating state for transmitting the sensor information, and returning the wireless terminal to the suspended state after completing the transmission of the base station information and sensor information.
摘要翻译：提供了一种通信方法，其可以在系统中可靠地将信息从基站发送到无线终端，该系统可以通过断电操作减少功率消耗，其中无线终端通过电源接通和断开重复操作状态和暂停状态，并且基站车站用于该方法。该方法包括以下步骤：将诸如提供给无线终端的命令或数据的基站信息存储在基站中，将无线终端从暂停状态传送到操作状态，以将信息从传感器传送到基站，耦合存储在基站中的基站信息到响应信号，以在传输传感器信息的操作状态下将其发送到无线终端，并且在完成基站信息和传感器的传输之后将无线终端返回到暂停状态信息。

65. 发明授权

US06949782B2 Semiconductor memories 失效
标题翻译：半导体存储器
公开(公告)号：US06949782B2
公开(公告)日：2005-09-27
申请号：US10790183
申请日：2004-03-02
申请人： Bryan Atwood , Kazuo Yano , Tomoyuki Ishii , Taro Osabe , Kazumasa Yanagisawa , Takeshi Sakata
发明人： Bryan Atwood , Kazuo Yano , Tomoyuki Ishii , Taro Osabe , Kazumasa Yanagisawa , Takeshi Sakata
IPC分类号： G11C11/00 , G11C11/401 , G11C11/405 , G11C11/406 , G11C11/4076 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L27/12
CPC分类号： H01L27/105 , G11C11/405 , G11C11/406 , G11C11/4076 , G11C2207/2281 , G11C2207/229 , H01L27/0207 , H01L27/108 , H01L27/1203
摘要： A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.
摘要翻译：本发明提供了高集成度的动态随机存取存储器。此外，提供了一种写入方法，使得减少了二晶体管和三晶体管增益单元存储器的单元尺寸。一种结合了作为写入元件的薄沟道晶体管的动态存储器，使得在本发明的存储器件中实现长的数据存储保持。通过本发明也实现了具有低操作功率和高密度的动态存储单元。

66. 发明申请

US20050032276A1 Semiconductor element and process for manufacturing the same 审中-公开
标题翻译：半导体元件及其制造方法
公开(公告)号：US20050032276A1
公开(公告)日：2005-02-10
申请号：US10936481
申请日：2004-09-09
申请人： Tomoyuki Ishii , Kazuo Yano , Koichi Seki , Toshiyuki Mine , Takashi Kobayashi
发明人： Tomoyuki Ishii , Kazuo Yano , Koichi Seki , Toshiyuki Mine , Takashi Kobayashi
IPC分类号： H01L27/115 , H01L27/12 , H01L29/68 , H01L29/788 , H01L21/00 , H01L21/82 , H01L21/8236
CPC分类号： H01L29/7887 , H01L27/115 , H01L27/1203 , H01L29/685 , H01L29/7883 , Y10S438/962
摘要： A semiconductor quantum memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against noises. In order to accomplish this a control electrode is formed so as to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size. A method of forming a memory element is also disclosed including performing the following steps of forming a first insulating layer, a second insulating layer, a first conductive layer and a layer of amorphous silicon. The amorphous silicon layer is crystallized to a polycrystalline silicon film. Semiconductor drains are deposited to form charge trapping and storage regions. A fourth insulating layer is deposited over the drains and a second conductive layer is deposited over a layer of silicon dioxide to form a control electrode of the memory element.
摘要翻译：公开了一种半导体量子存储器元件，其可以容易地在多个存储元件之间共享端子，并且可以通过高电流并且抵抗噪声。为了实现这一点，形成控制电极以覆盖连接低电阻区域的整个薄膜区域。因此，该元件可以具有小尺寸并且可以高密度地存储信息。因此，可以以减小的尺寸实现高度集成的低功耗非易失性存储器件。还公开了一种形成存储元件的方法，包括执行以下步骤：形成第一绝缘层，第二绝缘层，第一导电层和非晶硅层。非晶硅层结晶成多晶硅膜。沉积半导体漏极以形成电荷捕获和存储区域。在漏极上沉积第四绝缘层，并且在二氧化硅层上沉积第二导电层以形成存储元件的控制电极。

67. 发明申请

US20050023615A1 Semiconductor element and semiconductor memory device using the same 失效
标题翻译：半导体元件和使用其的半导体存储器件
公开(公告)号：US20050023615A1
公开(公告)日：2005-02-03
申请号：US10929424
申请日：2004-08-31
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L21/8247 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/04 , G11C16/28 , H01L21/28 , H01L21/336 , H01L27/01 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/66 , H01L29/76 , H01L29/788 , H01L29/792 , H01L29/94 , H01L31/036 , H01L31/062 , H01L31/112 , H01L31/113
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.
摘要翻译：一种场效应半导体元件，其具有较少数量的元件和减小的面积，并能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。

68. 发明授权

US06769110B2 Semiconductor integrated circuit device, storage medium on which cell library is stored and designing method for semiconductor integrated circuit 有权
标题翻译：半导体集成电路器件，其上存储有单元库的存储介质和用于半导体集成电路的设计方法
公开(公告)号：US06769110B2
公开(公告)日：2004-07-27
申请号：US10084435
申请日：2002-02-28
申请人： Naoki Katoh , Kazuo Yano , Yohei Akita , Mitsuru Hiraki
发明人： Naoki Katoh , Kazuo Yano , Yohei Akita , Mitsuru Hiraki
IPC分类号： G06F1750
CPC分类号： H03K19/1731 , G06F17/505 , H03K19/0013
摘要： This invention provides a storage medium on which there is stored a cell library to design a semiconductor integrated circuit to satisfy low power consumption and high speed operation and a design method using the cell library. The cell library is registered with at least two kinds of cells which are different in delay and power consumption while having the same function and the same shape. To satisfy the specification of the semiconductor integrated circuit, one cell is selected from at least two kinds of cells of the cell library.
摘要翻译：本发明提供了一种存储介质，其上存储有一个单元库以设计半导体集成电路以满足低功耗和高速操作，以及使用该单元库的设计方法。细胞库与具有相同功能和相同形状的延迟和功耗不同的至少两种细胞登记。为了满足半导体集成电路的规格，从单元库的至少两种单元中选择一个单元。

69. 发明授权

US06690206B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06690206B2
公开(公告)日：2004-02-10
申请号：US10052251
申请日：2002-01-23
申请人： Kunihito Rikino , Yasuhiko Sasaki , Kazuo Yano , Naoki Kato
发明人： Kunihito Rikino , Yasuhiko Sasaki , Kazuo Yano , Naoki Kato
IPC分类号： H03K19094
CPC分类号： H01L27/092 , H01L27/0203 , H03K19/1737
摘要： A pass-transistor logic circuit configuration that can form a high-speed chip in a small area with short wire length. In a selector circuit PMOS and NMOS transistors with different gate signals but with the same drain outputs are arranged, respectively, so their diffusion layers are shared. The PMOS and NMOS are staggered so that their gates are almost in line. With this arrangement, wires connecting drains of the PMOS and NMOS and wires connecting sources of the PMOS and NMOS do not intersect each other, so they can be wired with only the first wiring layer. Further, gate input signals can be wired with only polysilicon wires without crossing each other. The pass-transistor logic circuit is made to pass through the signal buffers before or after it is connected to the selector. This can make a compact, fast circuit.
摘要翻译：通过晶体管逻辑电路配置，可以在短的线长度的小区域内形成高速芯片。在选择器电路中，分别布置具有不同栅极信号但具有相同漏极输出的PMOS和NMOS晶体管，因此它们的扩散层被共享。 PMOS和NMOS交错，使得它们的栅极几乎成一行。通过这种布置，连接PMOS和NMOS的漏极的电线和连接PMOS和NMOS的源极的线彼此不相交，因此它们可以仅与第一布线层布线。此外，栅极输入信号可以仅连接多晶硅线，而不会彼此交叉。通过晶体管逻辑电路在连接到选择器之前或之后通过信号缓冲器。这可以使紧凑，快速的电路。

70. 发明授权

US06651223B2 Logic circuit design method and cell library for use therewith 失效
公开(公告)号：US06651223B2
公开(公告)日：2003-11-18
申请号：US10287599
申请日：2002-11-05
申请人： Shunzo Yamashita , Kazuo Yano , Naoki Kato
发明人： Shunzo Yamashita , Kazuo Yano , Naoki Kato
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A method, system, and library for generating high-speed logic circuits with reduced path depths even in cases when a critical path diverges into a plurality of paths that eventually converge. By replacing the gates of a logic circuit by selectors with two inputs and one output, a selector-based circuit is generated where a local circuit between the path divergence node and convergence node is detected. The stages of the critical path are reduced by replacing the local circuit by a logically equivalent selector with two inputs and one output; wherein one input of the selector is controlled by a circuit formed by inputting a logical value of “0” to the divergence node from which the local circuit is developed and a second input of the selector is controlled by a circuit formed by inputting a logical value of “1” to the divergence node.

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