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1. 发明授权

US06356118B1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06356118B1
公开(公告)日：2002-03-12
申请号：US09549711
申请日：2000-04-14
申请人： Kunihito Rikino , Yasuhiko Sasaki , Kazuo Yano , Naoki Kato
发明人： Kunihito Rikino , Yasuhiko Sasaki , Kazuo Yano , Naoki Kato
IPC分类号： H03K19094
CPC分类号： H01L27/092 , H01L27/0203 , H03K19/1737
摘要： A pass-transistor logic circuit configuration that can form a high-speed chip in a small area with short wire length. In a selector circuit PMOS and NMOS transistors with different gate signals but with the same drain outputs are arranged, respectively, so their diffusion layers are shared. The PMOS and NMOS are staggered so that their gates are almost in line. With this arrangement, wires connecting drains of the PMOS and NMOS and wires connecting sources of the PMOS and NMOS do not intersect each other, so they can be wired with only the first wiring layer. Further, gate input signals can be wired with only polysilicon wires without crossing each other. The pass-transistor logic circuit is made to pass through the signal buffers before or after it is connected to the selector. This can make a compact, fast circuit.
摘要翻译：通过晶体管逻辑电路配置，可以在短的线长度的小区域内形成高速芯片。在选择器电路中，分别布置具有不同栅极信号但具有相同漏极输出的PMOS和NMOS晶体管，因此它们的扩散层被共享。 PMOS和NMOS交错，使得它们的栅极几乎成一行。通过这种布置，连接PMOS和NMOS的漏极的电线和连接PMOS和NMOS的源极的线彼此不相交，因此它们可以仅与第一布线层布线。此外，栅极输入信号可以仅连接多晶硅线，而不会彼此交叉。通过晶体管逻辑电路在连接到选择器之前或之后通过信号缓冲器。这可以使紧凑，快速的电路。

2. 发明授权

US06445214B2 Semiconductor integrated circuit 失效
公开(公告)号：US06445214B2
公开(公告)日：2002-09-03
申请号：US09956996
申请日：2001-09-21
申请人： Yasuhiko Sasaki , Kunihito Rikino , Kazuo Yano , Shunzo Yamashita
发明人： Yasuhiko Sasaki , Kunihito Rikino , Kazuo Yano , Shunzo Yamashita
IPC分类号： H01L2710
CPC分类号： H01L27/11803 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends, a signal polarity inverting circuit is laid out in the cell and the arrangement of wells is different from the arrangement of a conventional CMOS logic circuit.

3. 发明授权

US06690206B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06690206B2
公开(公告)日：2004-02-10
申请号：US10052251
申请日：2002-01-23
申请人： Kunihito Rikino , Yasuhiko Sasaki , Kazuo Yano , Naoki Kato
发明人： Kunihito Rikino , Yasuhiko Sasaki , Kazuo Yano , Naoki Kato
IPC分类号： H03K19094
CPC分类号： H01L27/092 , H01L27/0203 , H03K19/1737
摘要： A pass-transistor logic circuit configuration that can form a high-speed chip in a small area with short wire length. In a selector circuit PMOS and NMOS transistors with different gate signals but with the same drain outputs are arranged, respectively, so their diffusion layers are shared. The PMOS and NMOS are staggered so that their gates are almost in line. With this arrangement, wires connecting drains of the PMOS and NMOS and wires connecting sources of the PMOS and NMOS do not intersect each other, so they can be wired with only the first wiring layer. Further, gate input signals can be wired with only polysilicon wires without crossing each other. The pass-transistor logic circuit is made to pass through the signal buffers before or after it is connected to the selector. This can make a compact, fast circuit.
摘要翻译：通过晶体管逻辑电路配置，可以在短的线长度的小区域内形成高速芯片。在选择器电路中，分别布置具有不同栅极信号但具有相同漏极输出的PMOS和NMOS晶体管，因此它们的扩散层被共享。 PMOS和NMOS交错，使得它们的栅极几乎成一行。通过这种布置，连接PMOS和NMOS的漏极的电线和连接PMOS和NMOS的源极的线彼此不相交，因此它们可以仅与第一布线层布线。此外，栅极输入信号可以仅连接多晶硅线，而不会彼此交叉。通过晶体管逻辑电路在连接到选择器之前或之后通过信号缓冲器。这可以使紧凑，快速的电路。

4. 发明授权

US06313665B1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06313665B1
公开(公告)日：2001-11-06
申请号：US09402648
申请日：2000-02-03
申请人： Yasuhiko Sasaki , Kunihito Rikino , Kazuo Yano , Shunzo Yamashita
发明人： Yasuhiko Sasaki , Kunihito Rikino , Kazuo Yano , Shunzo Yamashita
IPC分类号： H01L2710
CPC分类号： H03K19/1737 , H01L27/0207 , H01L27/11898
摘要： The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends, a signal polarity inverting circuit is laid out in the cell and the arrangement of wells is different from the arrangement of a conventional CMOS logic circuit.
摘要翻译：传输晶体管逻辑电路单元的I / O端子位置分布在单元中，输出放大器设置在单元的端部，传输晶体管电路沿电位线延伸的方向排列，信号极性反转电路布置在单元中，并且阱的布置不同于传统CMOS逻辑电路的布置。

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