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1. 发明授权

US06356118B1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06356118B1
公开(公告)日：2002-03-12
申请号：US09549711
申请日：2000-04-14
申请人： Kunihito Rikino , Yasuhiko Sasaki , Kazuo Yano , Naoki Kato
发明人： Kunihito Rikino , Yasuhiko Sasaki , Kazuo Yano , Naoki Kato
IPC分类号： H03K19094
CPC分类号： H01L27/092 , H01L27/0203 , H03K19/1737
摘要： A pass-transistor logic circuit configuration that can form a high-speed chip in a small area with short wire length. In a selector circuit PMOS and NMOS transistors with different gate signals but with the same drain outputs are arranged, respectively, so their diffusion layers are shared. The PMOS and NMOS are staggered so that their gates are almost in line. With this arrangement, wires connecting drains of the PMOS and NMOS and wires connecting sources of the PMOS and NMOS do not intersect each other, so they can be wired with only the first wiring layer. Further, gate input signals can be wired with only polysilicon wires without crossing each other. The pass-transistor logic circuit is made to pass through the signal buffers before or after it is connected to the selector. This can make a compact, fast circuit.
摘要翻译：通过晶体管逻辑电路配置，可以在短的线长度的小区域内形成高速芯片。在选择器电路中，分别布置具有不同栅极信号但具有相同漏极输出的PMOS和NMOS晶体管，因此它们的扩散层被共享。 PMOS和NMOS交错，使得它们的栅极几乎成一行。通过这种布置，连接PMOS和NMOS的漏极的电线和连接PMOS和NMOS的源极的线彼此不相交，因此它们可以仅与第一布线层布线。此外，栅极输入信号可以仅连接多晶硅线，而不会彼此交叉。通过晶体管逻辑电路在连接到选择器之前或之后通过信号缓冲器。这可以使紧凑，快速的电路。

2. 发明授权

US06690206B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06690206B2
公开(公告)日：2004-02-10
申请号：US10052251
申请日：2002-01-23
申请人： Kunihito Rikino , Yasuhiko Sasaki , Kazuo Yano , Naoki Kato
发明人： Kunihito Rikino , Yasuhiko Sasaki , Kazuo Yano , Naoki Kato
IPC分类号： H03K19094
CPC分类号： H01L27/092 , H01L27/0203 , H03K19/1737
摘要： A pass-transistor logic circuit configuration that can form a high-speed chip in a small area with short wire length. In a selector circuit PMOS and NMOS transistors with different gate signals but with the same drain outputs are arranged, respectively, so their diffusion layers are shared. The PMOS and NMOS are staggered so that their gates are almost in line. With this arrangement, wires connecting drains of the PMOS and NMOS and wires connecting sources of the PMOS and NMOS do not intersect each other, so they can be wired with only the first wiring layer. Further, gate input signals can be wired with only polysilicon wires without crossing each other. The pass-transistor logic circuit is made to pass through the signal buffers before or after it is connected to the selector. This can make a compact, fast circuit.
摘要翻译：通过晶体管逻辑电路配置，可以在短的线长度的小区域内形成高速芯片。在选择器电路中，分别布置具有不同栅极信号但具有相同漏极输出的PMOS和NMOS晶体管，因此它们的扩散层被共享。 PMOS和NMOS交错，使得它们的栅极几乎成一行。通过这种布置，连接PMOS和NMOS的漏极的电线和连接PMOS和NMOS的源极的线彼此不相交，因此它们可以仅与第一布线层布线。此外，栅极输入信号可以仅连接多晶硅线，而不会彼此交叉。通过晶体管逻辑电路在连接到选择器之前或之后通过信号缓冲器。这可以使紧凑，快速的电路。

3. 发明授权

US06445214B2 Semiconductor integrated circuit 失效
公开(公告)号：US06445214B2
公开(公告)日：2002-09-03
申请号：US09956996
申请日：2001-09-21
申请人： Yasuhiko Sasaki , Kunihito Rikino , Kazuo Yano , Shunzo Yamashita
发明人： Yasuhiko Sasaki , Kunihito Rikino , Kazuo Yano , Shunzo Yamashita
IPC分类号： H01L2710
CPC分类号： H01L27/11803 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends, a signal polarity inverting circuit is laid out in the cell and the arrangement of wells is different from the arrangement of a conventional CMOS logic circuit.

4. 发明授权

US06313665B1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06313665B1
公开(公告)日：2001-11-06
申请号：US09402648
申请日：2000-02-03
申请人： Yasuhiko Sasaki , Kunihito Rikino , Kazuo Yano , Shunzo Yamashita
发明人： Yasuhiko Sasaki , Kunihito Rikino , Kazuo Yano , Shunzo Yamashita
IPC分类号： H01L2710
CPC分类号： H03K19/1737 , H01L27/0207 , H01L27/11898
摘要： The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends, a signal polarity inverting circuit is laid out in the cell and the arrangement of wells is different from the arrangement of a conventional CMOS logic circuit.
摘要翻译：传输晶体管逻辑电路单元的I / O端子位置分布在单元中，输出放大器设置在单元的端部，传输晶体管电路沿电位线延伸的方向排列，信号极性反转电路布置在单元中，并且阱的布置不同于传统CMOS逻辑电路的布置。

5. 发明授权

US06845349B1 Method for designing semiconductor integrated circuit and automatic designing device 失效
标题翻译：半导体集成电路设计方法及自动设计装置
公开(公告)号：US06845349B1
公开(公告)日：2005-01-18
申请号：US09659735
申请日：2000-09-11
申请人： Yasuhiko Sasaki , Kazuo Yano , Shunzo Yamashita , Koichi Seki
发明人： Yasuhiko Sasaki , Kazuo Yano , Shunzo Yamashita , Koichi Seki
IPC分类号： G06F17/50 , H03K19/173 , G06G7/62
CPC分类号： H03K19/1737 , G06F17/505 , H03K19/1736
摘要： A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced. The program executes the following steps: a) receiving inputted logic functions which define the logical relationship between the inputs and the outputs, and an inputted target specification, b) generating a binary decision diagram from part of the logic functions received at (a), c) replacing the diagram nodes formed at (b) with pass transistor circuit, d) judging whether or not the simulation characteristics of the pass transistor circuit described in (c) meets the target specification described in (a), and executing the following steps when the judgment is “no”, e) replacing part of the diagram generated by the procedure described in (b) with another diagram, f) allocating a new binary decision diagram to the control inputs of the nodes of the replaced diagram prepared at (e), and g) repeating the steps (c) and (d) for the diagram prepared at (f).
摘要翻译：用于自动设计用于设计传输晶体管电路的方法的逻辑电路的程序，由此降低了所需晶体管的数量，延迟时间，功耗以及传输晶体管电路的芯片面积。该程序执行以下步骤：a）接收定义输入和输出之间的逻辑关系的输入逻辑功能以及输入的目标规范，b）从（a）中接收的部分逻辑函数生成二进制判定图， c）用传统晶体管电路代替（b）形成的图形节点，d）判断（c）中描述的传输晶体管电路的仿真特性是否满足（a）中描述的目标规范，并执行以下步骤当判断为“否”时，e）用另一个图替换由（b）中描述的过程产生的图的一部分，f）将新的二进制决策图分配给在 e），g）对（f）制备的图重复步骤（c）和（d）。

6. 发明授权

US06486708B2 Logic circuit and its forming method 有权
公开(公告)号：US06486708B2
公开(公告)日：2002-11-26
申请号：US10122385
申请日：2002-04-16
申请人： Shunzo Yamashita , Kazuo Yano , Yasuhiko Sasaki
发明人： Shunzo Yamashita , Kazuo Yano , Yasuhiko Sasaki
IPC分类号： H03K19094
CPC分类号： G06F17/505 , H03K19/1737
摘要： This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

7. 发明授权

US06323690B1 Logic circuit and its forming method 失效
公开(公告)号：US06323690B1
公开(公告)日：2001-11-27
申请号：US09610697
申请日：2000-07-05
申请人： Shunzo Yamashita , Kazuo Yano , Yasuhiko Sasaki
发明人： Shunzo Yamashita , Kazuo Yano , Yasuhiko Sasaki
IPC分类号： H03K19094
CPC分类号： G06F17/505 , H03K19/1737
摘要： This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

8. 发明授权

US06260185B1 Method for designing semiconductor integrated circuit and automatic designing device 失效
标题翻译：半导体集成电路设计方法及自动设计装置
公开(公告)号：US06260185B1
公开(公告)日：2001-07-10
申请号：US08930219
申请日：1997-10-20
申请人： Yasuhiko Sasaki , Kazuo Yano , Shunzo Yamashita , Koichi Seki
发明人： Yasuhiko Sasaki , Kazuo Yano , Shunzo Yamashita , Koichi Seki
IPC分类号： G06G748
CPC分类号： G06F17/505 , H03K19/1736 , H03K19/1737
摘要： A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced. The program executes the following steps: a) receiving inputted logic functions which define the logical relationship between the inputs and the outputs, and an inputted target specification, b) generating a binary decision diagram from part of the logic functions received at (a), c) replacing the diagram nodes formed at (b) with pass transistor circuit, d) judging whether or not the simulation characteristics of the pass transistor circuit described in (c) meets the target specification described in (a), and executing the following steps when the judgment is “no”, e) replacing part of the diagram generated by the procedure described in (b) with another diagram, f) allocating a new binary decision diagram to the control inputs of the nodes of the replaced diagram prepared at (e), and g) repeating the steps (c) and (d) for the diagram prepared at (f).
摘要翻译：用于自动设计用于设计传输晶体管电路的方法的逻辑电路的程序，由此降低了所需晶体管的数量，延迟时间，功耗以及传输晶体管电路的芯片面积。该程序执行以下步骤：a）接收定义输入和输出之间的逻辑关系的输入逻辑功能以及输入的目标规范，b）从（a）中接收的部分逻辑函数生成二进制判定图， c）用传统晶体管电路代替（b）形成的图形节点，d）判断（c）中描述的传输晶体管电路的仿真特性是否满足（a）中描述的目标规范，并执行以下步骤当判断为“否”时，e）用另一个图替换由（b）中描述的过程产生的图的一部分，f）将新的二进制决策图分配给在 e），g）对（f）制备的图重复步骤（c）和（d）。

9. 发明授权

US5923189A Semiconductor integrated circuit comprised of pass-transistor circuits with different mutual connections 失效
标题翻译：半导体集成电路由具有不同相互连接的通过晶体管电路组成
公开(公告)号：US5923189A
公开(公告)日：1999-07-13
申请号：US633053
申请日：1996-04-16
申请人： Yasuhiko Sasaki , Kazuo Yano , Shunzo Yamashita , Koichi Seki
发明人： Yasuhiko Sasaki , Kazuo Yano , Shunzo Yamashita , Koichi Seki
IPC分类号： G06F17/50 , H03K19/173 , H03K19/0948
CPC分类号： H03K19/1736 , G06F17/505 , H03K19/1737
摘要： For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.
摘要翻译：对于第一和第二通过晶体管电路（PT1，PT2）之间的关系，前级的输出信号被提供给后级的栅极，并且对于第二和第三通过晶体管电路之间的关系（PT2，PT3），将前级的输出信号提供给后级的源极 - 漏极路径。第一通过晶体管电路（PT1）在第一输入节点（In1）和第二输入节点（In2）上接收逻辑上彼此独立的第一输入信号和第二输入信号。该逻辑电路需要较少数量的晶体管，并且能够降低功耗并延迟并完成复杂的逻辑功能。

10. 发明授权

US5872716A Semiconductor integrated logic circuit device using a pass transistor 失效
公开(公告)号：US5872716A
公开(公告)日：1999-02-16
申请号：US703189
申请日：1996-08-26
申请人： Kazuo Yano , Yasuhiko Sasaki
发明人： Kazuo Yano , Yasuhiko Sasaki
IPC分类号： H01L21/82 , H01L27/02 , H01L27/118 , H03K19/173 , G06F13/00
CPC分类号： H03K19/1735 , H01L27/0207 , H01L27/11807 , H01L2924/14
摘要： The semiconductor integrated circuit enjoys a high performance and can be produced at a low production cost and within a short time. A cell has an internal circuit connection such that an output terminal is connected to a plurality of input terminals through source-drain paths of active devices connected in the tree form, and gate electrodes of the active devices are connected to other input terminals. Two such cells having the same internal circuit connection, the same disposition of the internal circuit devices and the same disposition of the input/output terminals are disposed on the same chip, and mutually different logics can be accomplished by changing the form of application of input signals from outside the cells to the input terminals. A chip area of an integrated circuit designed by CAD using a cell library can be reduced and a high speed circuit operation can be attained. The present invention provides remarkable effect for improving performance of an ASIC, a microprocessor, etc., and for reducing the cost of production.

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