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61. 发明授权

US07365399B2 Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost 有权
标题翻译：用于形成半导体上孔（SOP）的结构和方法，用于高器件性能和低制造成本
公开(公告)号：US07365399B2
公开(公告)日：2008-04-29
申请号：US11333074
申请日：2006-01-17
申请人： Joel P. de Souza , Keith E. Fogel , Brian J. Greene , Devendra K. Sadana , Haining S. Yang
发明人： Joel P. de Souza , Keith E. Fogel , Brian J. Greene , Devendra K. Sadana , Haining S. Yang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/32 , H01L21/0203 , H01L21/76259 , H01L29/1033 , H01L29/1083 , H01L29/16 , H01L29/78
摘要： A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.
摘要翻译：提供了具有现有技术的SOI衬底的所有优点的半导体材料，包括例如低寄生电容和泄漏，而不具有浮体效应。更具体地说，本发明提供一种包括顶部半导体层和底部半导体层的半导体激光器（SOP）材料，其中半导体层通过多孔半导体材料在至少一个区域中分离。还提供了包括作为基板的SOP材料的半导体结构以及制造SOP材料的方法。该方法包括：形成具有第一半导体层的p型区域，将p型区域转换为多孔半导体材料，通过退火密封多孔半导体材料的上表面，以及在多孔半导体材料的顶部形成第二半导体层。

62. 发明申请

US20080057653A1 METHOD AND STRUCTURE FOR IMPROVING DEVICE PERFORMANCE VARIATION IN DUAL STRESS LINER TECHNOLOGY 有权
标题翻译：改进双应力衬管技术中设备性能变化的方法与结构
公开(公告)号：US20080057653A1
公开(公告)日：2008-03-06
申请号：US11468402
申请日：2006-08-30
申请人： Dureseti Chidambarrao , Brian J. Greene
发明人： Dureseti Chidambarrao , Brian J. Greene
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823412 , H01L27/088 , H01L27/092 , H01L29/7842 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A method and semiconductor structure that overcome the dual stress liner boundary problem, without significantly increasing the overall size of the integrated circuit, are provided. In accordance with the present invention, the dual stress liner boundary or gap therebetween is forced to land on a neighboring dummy gate region. By forcing the dual stress liner boundary or gap between the liners to land on the dummy gate region, the large stresses associated with the dual stress liner boundary or gap are transferred to the dummy gate region, not the semiconductor substrate. Thus, the impact of the dual stress liner boundary on the nearest neighboring FET is reduced. Additionally, benefits of device variability and packing density are achieved utilizing the present invention.
摘要翻译：提供了克服双应力衬垫边界问题的方法和半导体结构，而不显着增加集成电路的总体尺寸。根据本发明，它们之间的双应力衬垫边界或间隙被迫在邻近的虚拟栅极区域上着陆。通过迫使衬垫之间的双重应力衬垫边界或间隙落在虚拟栅极区上，与双应力衬垫边界或间隙相关联的大应力被传递到虚拟栅极区而不是半导体衬底。因此，双应力衬垫边界对最近的相邻FET的影响减小。此外，利用本发明实现了装置可变性和包装密度的益处。

63. 发明申请

US20070161244A1 METHOD AND APPARATUS FOR POST SILICIDE SPACER REMOVAL 有权
标题翻译：硅胶分离器去除后的方法和装置
公开(公告)号：US20070161244A1
公开(公告)日：2007-07-12
申请号：US11164417
申请日：2005-11-22
申请人： Brian J. Greene , Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Siddhartha Panda , Kern Rim , Young Way Teh
发明人： Brian J. Greene , Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Siddhartha Panda , Kern Rim , Young Way Teh
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/31144 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.
摘要翻译：后硅化物间隔物去除的方法（和装置）包括通过使用氧化物层和氮化物层中的至少一种来防止对硅化物间隔物的损害。

64. 发明授权

US08785291B2 Post-gate shallow trench isolation structure formation 有权
公开(公告)号：US08785291B2
公开(公告)日：2014-07-22
申请号：US13277259
申请日：2011-10-20
申请人： Xiaojun Yu , Brian J. Greene , Yue Liang
发明人： Xiaojun Yu , Brian J. Greene , Yue Liang
IPC分类号： H01L21/76
CPC分类号： H01L29/0653 , H01L21/76224 , H01L21/76801 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/78 , H01L29/7834
摘要： Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.

65. 发明授权

US08629501B2 Stress-generating structure for semiconductor-on-insulator devices 有权
标题翻译：绝缘体上半导体器件的应力产生结构
公开(公告)号：US08629501B2
公开(公告)日：2014-01-14
申请号：US13370898
申请日：2012-02-10
申请人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
发明人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
IPC分类号： H01L27/12
CPC分类号： H01L29/0603 , H01L21/76224 , H01L29/1025 , H01L29/1054 , H01L29/84
摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
摘要翻译：在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。氧化硅材料沉积在深沟槽中，平坦化和凹陷。去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

66. 发明授权

US08598009B2 Self-aligned embedded SiGe structure and method of manufacturing the same 失效
标题翻译：自对准嵌入式SiGe结构及其制造方法
公开(公告)号：US08598009B2
公开(公告)日：2013-12-03
申请号：US13456633
申请日：2012-04-26
申请人： Brian J. Greene , William K. Henson , Judson R. Holt , Michael D. Steigerwalt , Kuldeep Amarnath , Rohit Pal , Johan W. Weijtmans
发明人： Brian J. Greene , William K. Henson , Judson R. Holt , Michael D. Steigerwalt , Kuldeep Amarnath , Rohit Pal , Johan W. Weijtmans
IPC分类号： H01L21/8222
CPC分类号： H01L29/66636 , H01L21/3247 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/7848
摘要： A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.
摘要翻译：低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

67. 发明申请

US20130099281A1 POST-GATE SHALLOW TRENCH ISOLATION STRUCTURE FORMATION 有权
标题翻译：后门隔离分离结构形成
公开(公告)号：US20130099281A1
公开(公告)日：2013-04-25
申请号：US13277259
申请日：2011-10-20
申请人： Xiaojun Yu , Brian J. Greene , Yue Liang
发明人： Xiaojun Yu , Brian J. Greene , Yue Liang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0653 , H01L21/76224 , H01L21/76801 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/78 , H01L29/7834
摘要： Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.
摘要翻译：掺杂的阱，栅极堆叠和嵌入的源极和漏极区域形成在半导体衬底上或之中，随后在半导体衬底中形成浅沟槽。可以通过在掺杂阱，栅极堆叠和嵌入的源极和漏极区域上形成平坦化材料层来形成浅沟槽; 图案化平坦化材料层; 并将平坦化材料层中的图案转移到栅极堆叠，嵌入的源极和漏极区以及掺杂阱中。浅沟槽用电介质材料填充以形成浅沟槽隔离结构。或者，可以通过在掺杂阱，栅极堆叠以及嵌入的源极和漏极区域上施加光刻胶，然后蚀刻下面的结构的暴露部分来形成浅沟槽。去除光致抗蚀剂后，可以通过填充浅沟槽形成浅沟槽隔离结构。

68. 发明申请

US20130087832A1 Tucked Active Region Without Dummy Poly For Performance Boost and Variation Reduction 有权
标题翻译：没有虚拟聚合物的折叠活动区域用于性能提升和变化减少
公开(公告)号：US20130087832A1
公开(公告)日：2013-04-11
申请号：US13253375
申请日：2011-10-05
申请人： Xiaojun Yu , Brian J. Greene , Yue Liang
发明人： Xiaojun Yu , Brian J. Greene , Yue Liang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/02112 , H01L21/02532 , H01L21/28123 , H01L21/76224 , H01L29/0649 , H01L29/165 , H01L29/66545 , H01L29/66553 , H01L29/66568 , H01L29/66636
摘要： In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.
摘要翻译：在一个实施例中，提供了半导体器件，其包括半导体衬底，该半导体衬底包括有源区和位于有源区的周边的至少一个沟槽隔离区，以及存在于半导体衬底的有源区的一部分上的功能栅结构。嵌入式半导体区域存在于半导体衬底的有源区域中，在有源区域的存在功能栅极结构的部分的相对侧上。半导体衬底的有源区域的一部分将嵌入的半导体区域的最外边缘与至少一个隔离区域分开。还提供了形成上述装置的方法。

69. 发明授权

US08236661B2 Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage 有权
标题翻译：自对准井注入，用于改善短沟道效应控制，寄生电容和结漏电
公开(公告)号：US08236661B2
公开(公告)日：2012-08-07
申请号：US12568287
申请日：2009-09-28
申请人： Robert H. Dennard , Brian J. Greene , Zhibin Ren , Xinlin Wang
发明人： Robert H. Dennard , Brian J. Greene , Zhibin Ren , Xinlin Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L21/26586 , H01L21/823814 , H01L29/105 , H01L29/66492 , H01L29/66537 , H01L29/66545 , H01L29/66659 , H01L29/7848 , H01L29/78654 , H01L29/78696
摘要： A method of forming a self-aligned well implant for a transistor includes forming a patterned gate structure over a substrate, including a gate conductor, a gate dielectric layer and sidewall spacers, the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a doped semiconductor layer beneath the undoped semiconductor layer; removing portions of the undoped semiconductor layer and the doped semiconductor layer left unprotected by the patterned gate structure, wherein a remaining portion of the undoped semiconductor layer beneath the patterned gate structure defines a transistor channel and a remaining portion of the doped semiconductor layer beneath the patterned gate structure defines the self-aligned well implant; and growing a new semiconductor layer at locations corresponding to the removed portions of the undoped semiconductor layer and the doped semiconductor layer, the new semiconductor layer corresponding to source and drain regions of the transistor.
摘要翻译：形成用于晶体管的自对准阱注入的方法包括在衬底上形成图案化栅极结构，该衬底包括栅极导体，栅极电介质层和侧壁间隔物，所述衬底包括在栅极介电层下面的未掺杂的半导体层，以及未掺杂的半导体层下面的掺杂半导体层; 去除未图示的栅极结构保护的未掺杂半导体层和掺杂半导体层的部分，其中在图案化栅极结构下面的未掺杂半导体层的剩余部分限定晶体管沟道，并且掺杂半导体层的图案化下面的掺杂半导体层的剩余部分栅极结构定义了自对准阱植入物; 以及在对应于未掺杂半导体层和掺杂半导体层的去除部分的位置处生长新的半导体层，新的半导体层对应于晶体管的源极和漏极区域。

70. 发明授权

US08222673B2 Self-aligned embedded SiGe structure and method of manufacturing the same 失效
标题翻译：自对准嵌入式SiGe结构及其制造方法
公开(公告)号：US08222673B2
公开(公告)日：2012-07-17
申请号：US12795683
申请日：2010-06-08
申请人： Brian J. Greene , William K. Henson , Judson R. Holt , Michael D. Steigerwalt , Kuldeep Amarnath , Rohit Pal , Johan W. Weijtmans
发明人： Brian J. Greene , William K. Henson , Judson R. Holt , Michael D. Steigerwalt , Kuldeep Amarnath , Rohit Pal , Johan W. Weijtmans
IPC分类号： H01L21/02
CPC分类号： H01L29/66636 , H01L21/3247 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/7848
摘要： A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.
摘要翻译：低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

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