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    • 63. 发明授权
      US06286083B1 Computer system with adaptive memory arbitration scheme 失效
    • Computer system with adaptive memory arbitration scheme
    • 具有自适应内存仲裁方案的计算机系统
    • US06286083B1
    • 2001-09-04
    • US09112000
    • 1998-07-08
    • Kenneth T. Chin , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens , Michael J. Collins , C. Kevin Coffee
    • Kenneth T. Chin , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens , Michael J. Collins , C. Kevin Coffee
    • G06F1318
    • G06F13/1605
    • A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.
    • 计算机系统包括用于对存储器访问请求进行优先级的自适应存储器仲裁器，包括自调整可编程请求优先级排序系统。 存储器仲裁器在每个仲裁周期内进行调整，从而降低获取内存仲裁的任何请求的优先级。 因此，初始保持低优先级排序的存储器请求可以逐渐提前优先，直到该请求赢得存储器仲裁。 这样的方案可防止低优先级的设备变得“记忆不足”。 因为某些类型的存储器请求（例如刷新请求和存储器读取）固有地需要比其他请求（诸如存储器写入）更快的存储器访问，所以自适应存储器仲裁器另外将不可调整的优先级结构集成到自适应排名系统中，从而保证更快的服务 最迫切的要求。 此外，自适应存储器仲裁方案引入了可调整优先权重的灵活方法，其允许所选择的设备在没有丢失请求优先级的情况下处理可编程数量的连续存储器访问。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 65. 发明授权
      US06247102B1 Computer system employing memory controller and bridge interface permitting concurrent operation 失效
    • Computer system employing memory controller and bridge interface permitting concurrent operation
    • 采用内存控制器和桥接口的计算机系统允许并行运行
    • US06247102B1
    • 2001-06-12
    • US09047876
    • 1998-03-25
    • Kenneth T. Chin , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens , C. Kevin Coffee , Michael J. Collins , John Larson
    • Kenneth T. Chin , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens , C. Kevin Coffee , Michael J. Collins , John Larson
    • G06F1314
    • G06F13/1642 , G06F13/4036
    • A computer system includes a CPU, a memory device, two expansion buses, and a bridge logic unit coupling together the CPU, the memory device and the expansion buses. The CPU couples to the bridge logic unit via a CPU bus and the memory device couples to the bridge logic unit via a memory bus. The bridge logic unit generally routes bus cycle requests from one of the four buses to another of the buses while concurrently routing bus cycle requests to another pair of buses. The bridge logic unit preferably includes four interfaces, one each to the CPU, memory device and the two expansion buses. Each pair of interfaces are coupled by at least one queue; write requests are stored (or “posted”) in write queues and read data are stored in read queues. Because each interface can communicate concurrently with all other interfaces via the read and write queues, the possibility exists that a first interface cannot access a second interface because the second interface is busy processing read or write requests from a third interface, thus starving the first interface for access to the second interface. To remedy this starvation problem, the bridge logic unit prevents the third interface from posting additional write requests to its write queue, thereby permitting the first interface access to the second interface. Further, read cycles may be retried from one interface to allow another interface to complete its bus transactions.
    • 计算机系统包括CPU，存储器件，两个扩展总线以及将CPU，存储器件和扩展总线耦合在一起的桥逻辑单元。 CPU通过CPU总线耦合到桥逻辑单元，存储器件通过存储器总线耦合到桥逻辑单元。 桥接逻辑单元通常将总线周期请求从四条总线之一路由到另一条总线，同时将总线周期请求转发到另一对总线。 桥逻辑单元优选地包括四个接口，每个接口连接到CPU，存储设备和两个扩展总线。 每对接口由至少一个队列耦合; 写入请求在写入队列中被存储（或“发布”），并且读取数据被存储在读取队列中。 因为每个接口可以通过读写队列与所有其他接口同时进行通信，所以存在第一接口无法访问第二接口的可能性，因为第二接口正忙于处理来自第三接口的读或写请求，从而使第一接口 用于访问第二个接口。 为了解决这个饥饿问题，桥接逻辑单元防止第三接口向其写入队列发布额外的写入请求，从而允许第一接口访问第二接口。 此外，可以从一个接口重试读周期，以允许另一接口完成其总线事务。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 66. 发明授权
      US06160562A System and method for aligning an initial cache line of data read from local memory by an input/output device 有权
    • System and method for aligning an initial cache line of data read from local memory by an input/output device
    • 用于通过输入/输出设备对准从本地存储器读取的数据的初始高速缓存行的系统和方法
    • US06160562A
    • 2000-12-12
    • US135620
    • 1998-08-18
    • Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
    • Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
    • G06F12/08 , G06F13/40 , G06F13/14
    • G06F12/0879 , G06F13/404
    • A computer is provided having a bus interface unit coupled between a CPU bus, a PCI bus and/or a graphics bus. The bus interface unit includes controllers linked to the respective buses and further includes a plurality of queues placed within address and data paths linking the various controllers. An interface controller coupled between a peripheral bus (excluding the CPU local bus) determines if an address forwarded from a peripheral device is the first address within a sequence of addresses used to select a set of quad words constituting a cache line. If that address (i.e., target address) is not the first address (i.e., initial address) in that sequence, then the target address is modified so that it becomes the initial address in that sequence. An offset between the target address and the modified address is denoted as a count value. The initial address aligns the reads to a cacheline boundary and stores in successive order the quad words of the cacheline in the queue of the bus interface unit. Quad words arriving in the queue prior to a quad word attributed to the target address are discarded. This ensures the interface controller, and eventually the peripheral device, will read quad words in successive address order, and all subsequently read quad words will also be sent in successive order until the peripheral read transaction is complete.
    • 提供一种具有耦合在CPU总线，PCI总线和/或图形总线之间的总线接口单元的计算机。 总线接口单元包括链接到各个总线的控制器，还包括放置在连接各种控制器的地址和数据路径内的多个队列。 耦合在外围总线（不包括CPU本地总线）之间的接口控制器确定从外围设备转发的地址是否是用于选择构成高速缓存行的一组四字的地址序列内的第一地址。 如果该地址（即，目标地址）不是该序列中的第一地址（即，初始地址），则修改目标地址，使其成为该序列中的初始地址。 目标地址与修改地址之间的偏移量表示为计数值。 初始地址将读取对齐到高速缓存行边界，并以连续顺序存储总线接口单元队列中的高速缓存行的四个字。 在归因于目标地址的四字之前到达队列的四字被丢弃。 这确保接口控制器以及最终的外围设备将以连续的地址顺序读取四个字，并且所有随后读取的四字都将以连续的顺序发送，直到外设读取事务完成。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 67. 发明授权
      US5778433A Computer system including a first level write-back cache and a second level cache 失效
    • Computer system including a first level write-back cache and a second level cache
    • 计算机系统包括第一级回写高速缓存和第二级高速缓存
    • US5778433A
    • 1998-07-07
    • US665244
    • 1996-06-17
    • Michael J. Collins , Gary W. Thome
    • Michael J. Collins , Gary W. Thome
    • G06F12/08
    • G06F12/0804 , G06F12/0897
    • An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.
    • 一种用于在解码特殊冲洗确认周期时监视和解码处理器总线周期并刷新第二级高速缓存的装置。 CPU优选地包括内部高速缓存和用于接收命令CPU冲洗其内部高速缓存的信号的刷新输入。 通过执行任何必要的循环来刷新脏数据到主存储器后，CPU执行特殊的刷新确认周期，以通知外部设备冲洗过程已经完成。 缓存控制器检测刷新确认周期，并向第二级缓存提供刷新信号。 然后，缓存控制器向CPU提供周期信号的结束以指示冲洗周期已被确认。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 70. 发明授权
      US5634073A System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation 失效
    • System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation
    • 具有与不同类型的写入操作相关联的多个发布队列的系统，用于基于读取操作的类型选择性地检查一个队列
    • US5634073A
    • 1997-05-27
    • US324246
    • 1994-10-14
    • Michael J. Collins , Gary W. Thome , Michael P. Moriarty , Jens K. Ramsey , John E. Larson
    • Michael J. Collins , Gary W. Thome , Michael P. Moriarty , Jens K. Ramsey , John E. Larson
    • G06F12/08 , G06F13/16 , G06F13/00
    • G06F12/0831 , G06F13/1605 , G06F13/1642 , G06F13/1694
    • A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional DRAM cycle which are used to control state machine operations.
    • 存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。 内存一致性以两种不同的方式保持。 在PCI总线接受任何读操作之前，两个发送队列都必须为空。 内容可寻址存储器（CAM）被用作PCI到存储器队列。 当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。 如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。 为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。 存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。 存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。 存储器控制器包括多个寄存器，其指定用于控制状态机操作的常规DRAM周期的特定部分的时钟周期数。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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