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61. 发明授权

US5712195A Method for making via structure with metallic spacer 失效
标题翻译：用金属间隔物制作通孔结构的方法
公开(公告)号：US5712195A
公开(公告)日：1998-01-27
申请号：US712573
申请日：1996-09-12
申请人： Kuang-Yeh Chang
发明人： Kuang-Yeh Chang
IPC分类号： H01L23/522 , H01L21/28
CPC分类号： H01L23/5226 , H01L2924/0002
摘要： A conductive via structure establishes an electrical interconnection between two conductive layers in a semiconductor structure by connecting a first conductive layer on a semiconductor substrate to a second conductive layer by means of a conductive via structure extending through a non-conductive layer separating the two conductive layers. The non-conductive layer preferably includes a layer of spin-on-glass (SOG), and is provided with a via aperture therethrough. A conductive spacer, preferably of TiW, is fabricated within the via aperture in abutment with the walls of the via aperture. A second conductive layer is fabricated over the non-conductive layer, the conductive spacer, and within the via aperture, to establish the completed electrical interconnection. The via structure reduces out-gassing and chipping from the SOG layer, yet provides a low electrical resistance path between the two conductive layers.
摘要翻译：导电通孔结构通过将导电通孔结构延伸穿过分离两个导电层的非导电层，将半导体衬底中的第一导电层连接到第二导电层，从而在半导体结构中的两个导电层之间建立电互连。非导电层优选地包括旋涂玻璃（SOG）层，并且设置有穿过其中的通孔。优选地由TiW制成的导电隔离件在通孔孔内与通孔的壁邻接地制成。第二导电层制造在非导电层，导电间隔物和通孔孔内，以建立完整的电互连。通孔结构减少了SOG层的泄漏和碎裂，但在两个导电层之间提供了低电阻路径。

62. 发明授权

US5504364A CMOS locos isolation for self-aligned NPN BJT in a BiCMOS process 失效
标题翻译：在BiCMOS工艺中用于自对准NPN BJT的CMOS区域隔离
公开(公告)号：US5504364A
公开(公告)日：1996-04-02
申请号：US294783
申请日：1994-08-24
申请人： Kuang-Yeh Chang , Yi-Hen Wei
发明人： Kuang-Yeh Chang , Yi-Hen Wei
IPC分类号： H01L21/762 , H01L21/8249 , H01L27/02 , H01L21/265
CPC分类号： H01L21/76218 , H01L21/8249
摘要： A method of fabricating BiCMOS devices, and the resultant BiCMOS device, are disclosed. According to the present invention, over-etching to the substrate on the deposited polysilicon emitter is prevented by providing additional oxide beneath a polysilicon layer as an etch stop. Despite inclusion of an oxide to define an end-point during patterning of an emitter, fabrication complexity is reduced by avoiding additional SAT masking and oxidation steps.
摘要翻译：公开了一种制造BiCMOS器件的方法和所得到的BiCMOS器件。根据本发明，通过在多晶硅层下方提供附加氧化物作为蚀刻停止来防止沉积的多晶硅发射极上的衬底的过度蚀刻。尽管包含氧化物以在发射体的图案化期间限定端点，但是通过避免额外的SAT掩蔽和氧化步骤来降低制造复杂性。

63. 发明授权

US5493132A Integrated circuit contact barrier formation with ion implant 失效
标题翻译：具有离子注入的集成电路接触屏障形成
公开(公告)号：US5493132A
公开(公告)日：1996-02-20
申请号：US394221
申请日：1995-02-24
申请人： Hunter B. Brugge , Kuang-Yeh Chang , Felix Fujishiro , Chang-Ou Lee , Walter D. Parmantie
发明人： Hunter B. Brugge , Kuang-Yeh Chang , Felix Fujishiro , Chang-Ou Lee , Walter D. Parmantie
IPC分类号： H01L21/285 , H01L21/768 , H01L33/00
CPC分类号： H01L21/76895 , H01L21/28518 , H01L21/28568 , H01L21/76843 , H01L21/76855 , H01L21/76859
摘要： A titanium-tungsten barrier layer is sputtered after active areas of a CMOS structure are exposed. An ion implant through the barrier layer and into the active areas disrupts the boundaries between the barrier layer and the underlying active areas. The implant can involve argon or, alternatively, silicon. The resulting structure is annealed. A conductor layer of an aluminum-copper alloy is deposited. An antireflection coating of TiW is deposited. The three-layer structure is then photolithographically patterned to define contacts and local interconnects. The ion implant before anneal results in less contact resistance, which is particularly critical for the barrier layer boundary with positively doped active areas.
摘要翻译：在CMOS结构的有源区域暴露之后溅射钛 - 钨阻挡层。穿过阻挡层并进入有源区域的离子注入破坏了阻挡层和下面的有效区域之间的边界。植入物可以包括氩或者替代地，硅。所得结构退火。沉积铝 - 铜合金的导体层。沉积TiW的抗反射涂层。然后将三层结构光刻图案化以限定接触和局部互连。退火之前的离子注入导致更小的接触电阻，这对于具有正掺杂有源区的势垒层边界是特别关键的。

64. 发明授权

US5371393A EEPROM cell with improved tunneling properties 失效
标题翻译：具有改善隧道性能的EEPROM单元
公开(公告)号：US5371393A
公开(公告)日：1994-12-06
申请号：US221463
申请日：1994-04-01
申请人： Kuang-Yeh Chang , Subhash R. Nariani
发明人： Kuang-Yeh Chang , Subhash R. Nariani
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/78
CPC分类号： H01L21/28273 , Y10S438/981
摘要： The present invention is directed to a semiconductor memory device and a method for fabricating a semiconductor memory device, in particular a E.sup.2 PROM, having an improved tunnel area wherein electrons travel to and from a floating gate. The tunnel area is characterized by properties which lend to a relatively large number of programming and erasure cycles over the life of the E.sup.2 PROM. The tunnel area includes a tunneling gate which is fabricated via two implant stages. Because these two stages are separate from one another, each of the implant stages can be independently optimized to improve the properties of the tunnel area. Further, the windows used to define the implant regions are easily fabricated and are designed to facilitate formation of the implant regions. The method of defining the window lends to easy scaling of the process for advancing generations of technology.
摘要翻译：本发明涉及一种用于制造具有改进的隧道面积的半导体存储器件，特别是E2PROM的半导体存储器件和方法，其中电子行进到浮栅。隧道区域的特点是在E2PROM的使用寿命期间可以实现相对较多的编程和擦除循环。隧道区域包括通过两个植入阶段制造的隧道门。因为这两个阶段是彼此分开的，因此可以独立地优化每个植入阶段以改善隧道区域的性质。此外，用于限定植入区域的窗口容易制造并且被设计成有利于植入区域的形成。定义窗口的方法有助于轻松扩展用于推进世代技术的过程。

65. 发明授权

US5120679A Anti-fuse structures and methods for making same 失效
标题翻译：反熔丝结构及其制作方法
公开(公告)号：US5120679A
公开(公告)日：1992-06-09
申请号：US710220
申请日：1991-06-04
申请人： William J. Boardman , David P. Chan , Kuang-Yeh Chang , Calvin T. Gabriel , Vivek Jain , Subhash R. Nariani
发明人： William J. Boardman , David P. Chan , Kuang-Yeh Chang , Calvin T. Gabriel , Vivek Jain , Subhash R. Nariani
IPC分类号： H01L21/82 , H01L21/3205 , H01L23/52 , H01L23/525
CPC分类号： H01L23/5252 , H01L2924/0002 , Y10S148/055
摘要： An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, and oxide spacers lining the walls of a recess formed within the amorphous silicon. The spacers prevent failures of the anti-fuse structures by covering cusps formed in the amorphous silicon material. The method of the present invention forms the above-described anti-fuse structure and further solves the problem of removing unwanted spacer material from areas outside of the anti-fuse structure locations.
摘要翻译：一种抗熔丝结构，其特征在于基底，形成在其上形成有开口的基底上的氧化物层，设置在开口内并接触基底的非晶硅材料以及衬在非晶硅内形成的凹陷壁的氧化物间隔物。间隔物通过覆盖形成在非晶硅材料中的尖头来防止抗熔丝结构的故障。本发明的方法形成上述反熔丝结构，并且进一步解决了从抗熔丝结构位置之外的区域去除不想要的隔离材料的问题。

66. 发明授权

US4645562A Double layer photoresist technique for side-wall profile control in plasma etching processes 失效
标题翻译：用于等离子体蚀刻工艺中侧壁轮廓控制的双层光刻胶技术
公开(公告)号：US4645562A
公开(公告)日：1987-02-24
申请号：US728012
申请日：1985-04-29
申请人： Kuan Y. Liao , Kuang-Yeh Chang , Hsing-Chien Ma
发明人： Kuan Y. Liao , Kuang-Yeh Chang , Hsing-Chien Ma
IPC分类号： H01L21/302 , H01L21/027 , H01L21/3065 , H01L21/311 , H01L21/3213 , B44C1/22 , B29C17/08 , C03C15/00 , C03C25/06
CPC分类号： H01L21/32137 , H01L21/31116 , H01L21/31144 , H01L21/32136
摘要： A photolithographic process useful for VLSI fabrication is disclosed for achieving side-wall profile control of poly lines, metal lines, contact and via openings. Layers of a first and second photoresist materials are formed on the poly, metal or oxide-covered substrate. The top layer is patterned by conventional processes to define the final device geometry. The bottom layer is exposed and over-developed to form an overhang structure about the line pattern or the contact/via opening. During the subsequent anisotropic plasma-assisted etching step, some ions or particles are passed obliquely over the overhang and bombard the opening corner, the side-wall and the under-cut area. The plasma-assisted etching step not only forms the poly or metal lines, or the contact or via opening, but also results in an opening with rounded corners and a smoothly tapered side-wall profile. The subsequent metal film deposition step results in a uniform film thickness around the edges of the opening. The process thus alleviates the problem of high contact resistance previously encountered as a result of dry etching the contact or via openings.
摘要翻译：公开了一种用于VLSI制造的光刻工艺，用于实现多线，金属线，接触和通孔的侧壁轮廓控制。第一和第二光致抗蚀剂材料的层在多金属或氧化物覆盖的基底上形成。通过常规方法对顶层进行图案化以定义最终的装置几何形状。底层暴露并过度显影以形成围绕线图案或接触/通孔开口的悬垂结构。在随后的各向异性等离子体辅助蚀刻步骤中，一些离子或颗粒倾斜地穿过悬垂物并且轰击开口角，侧壁和下切区域。等离子体辅助蚀刻步骤不仅形成多个或金属线，或接触或通孔，而且还形成具有圆角和平滑锥形侧壁轮廓的开口。随后的金属膜沉积步骤导致围绕开口边缘的均匀的膜厚度。因此，该方法减轻了由于干蚀刻接触或通孔的结果而先前遇到的高接触电阻的问题。

67. 发明申请

US20090026576A1 ANTI-FUSE 审中-公开
标题翻译：防静电
公开(公告)号：US20090026576A1
公开(公告)日：2009-01-29
申请号：US11782154
申请日：2007-07-24
申请人： Kuang-Yeh Chang , Shing-Ren Sheu , Chung Jen Ho
发明人： Kuang-Yeh Chang , Shing-Ren Sheu , Chung Jen Ho
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L23/5252 , H01L21/26586 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse is provided. The anti-fuse includes a substrate, a gate disposed over the substrate, a gate dielectric layer sandwiched between the substrate and the gate, and two source/drain regions in the substrate at respective sides of the gate. The gate and the substrate have the same conductive type, but the conductive type of the gate and the substrate is different from that of the two source/drain regions.
摘要翻译：提供反熔丝。反熔丝包括衬底，设置在衬底上的栅极，夹在衬底和栅极之间的栅极电介质层以及在栅极的相应侧的衬底中的两个源极/漏极区域。栅极和衬底具有相同的导电类型，但是栅极和衬底的导电类型与两个源极/漏极区的导电类型不同。

68. 发明申请

US20070298620A1 SURFACE TREATMENT, SORTING AND ASSEMBLING METHODS OF MICROELECTRONIC DEVICES AND STORAGE STRUCTURE THEREOF 审中-公开
标题翻译：微电子器件的表面处理，分选和组装方法及其存储结构
公开(公告)号：US20070298620A1
公开(公告)日：2007-12-27
申请号：US11309142
申请日：2006-06-27
申请人： Kuang-Yeh Chang , Jin Yu
发明人： Kuang-Yeh Chang , Jin Yu
IPC分类号： H01L21/31
CPC分类号： H01L24/02 , H01L22/14 , H01L2924/01006 , H01L2924/01033 , H01L2924/3025
摘要： A storage structure for a microelectronic device including a chip which has completed all back-end-of-line (BEOL) processes and a solvent dissolvable polymer layer covering the surface of the chip. Since the surface of the chip is isolated from the external environment by the solvent dissolvable polymer layer, corrosion, discoloring or delamination of the chip can be avoided.
摘要翻译：一种微电子器件的存储结构，包括已经完成了所有后端（BEOL）工艺的芯片和覆盖芯片表面的溶剂可溶性聚合物层。由于芯片的表面通过溶剂可溶性聚合物层与外部环境隔离，因此可以避免芯片的腐蚀，变色或分层。

69. 发明申请

US20070010092A1 METHOD FOR ELIMINATING BRIDGING DEFECT IN VIA FIRST DUAL DAMASCENE PROCESS 有权
标题翻译：通过第一个双重DAMASCENE过程消除桥梁缺陷的方法
公开(公告)号：US20070010092A1
公开(公告)日：2007-01-11
申请号：US11160688
申请日：2005-07-06
申请人： Wen-Zhan Zhou , Hong Ma , Kuang-Yeh Chang
发明人： Wen-Zhan Zhou , Hong Ma , Kuang-Yeh Chang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/76816
摘要： A via-first dual damascene process is disclosed. When forming trench lines directly above two small pitched, dense via openings having diameter that is substantially equal to the line width of the trench lines, the trench photoresist is biased on the via openings to partially mask the sidewalls of the two dense via openings. By doing this, via-to-via bridging defects can be avoided.
摘要翻译：公开了一种通孔第一双镶嵌工艺。当直接在直径大约等于沟槽线的线宽度的两个小直径的密集通孔开口形成沟槽线时，沟槽光致抗蚀剂被偏置在通孔开口上以部分地掩蔽两个致密通孔的侧壁。通过这样做，可以避免通孔到通孔桥接缺陷。

70. 发明授权

US06303421B1 Method of manufacturing CMOS sensor 有权
标题翻译：制造CMOS传感器的方法
公开(公告)号：US06303421B1
公开(公告)日：2001-10-16
申请号：US09617565
申请日：2000-07-17
申请人： Kuang-Yeh Chang
发明人： Kuang-Yeh Chang
IPC分类号： H01L218238
CPC分类号： H01L21/823814 , H01L27/14609 , H01L27/14689
摘要： A method for manufacturing a CMOS sensor comprises the steps of providing a substrate having a first conductive type, wherein the substrate comprises an isolation region, an active region, a gate structure on the active region and a source/drain region having a second conductive type in the substrate. A patterned photoresist is formed over the substrate. A first doped region having the second conductive type is formed across a portion of the source/drain region and extends from the surface of the substrate into the substrate. A second doped region having the first conductive type is formed to wrap the first doped region in the substrate. A third doped region having the second conductive type is formed under the second doped region. A fourth doped region having the first conductive type is formed under the third doped region. The patterned photoresist is removed.
摘要翻译：一种用于制造CMOS传感器的方法包括以下步骤：提供具有第一导电类型的衬底，其中衬底包括隔离区，有源区，有源区上的栅极结构和具有第二导电类型的源极/漏极区在基材中。在衬底上形成图案化的光致抗蚀剂。具有第二导电类型的第一掺杂区跨越源/漏区的一部分形成并且从衬底的表面延伸到衬底中。形成具有第一导电类型的第二掺杂区域以包裹衬底中的第一掺杂区域。具有第二导电类型的第三掺杂区形成在第二掺杂区的下方。具有第一导电类型的第四掺杂区形成在第三掺杂区下。去除图案化的光致抗蚀剂。

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