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61. 发明申请

US20080220592A1 SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND SUBSTRATE PLANARIZATION METHOD 审中-公开
标题翻译：基板处理装置，基板处理方法和基板平面化方法
公开(公告)号：US20080220592A1
公开(公告)日：2008-09-11
申请号：US12045321
申请日：2008-03-10
申请人： Tadahiro Ohmi , Shigetoshi Sugawa , Masaki Hirayama , Tetsuya Goto
发明人： Tadahiro Ohmi , Shigetoshi Sugawa , Masaki Hirayama , Tetsuya Goto
IPC分类号： H01L21/3213 , H01L21/321
CPC分类号： H01L21/67115 , H01L21/3003 , H01L21/324 , H01L21/67098 , H01L21/67109 , H01L27/1214 , H01L27/127 , H01L29/66757 , H01L29/78603
摘要： A substrate processing apparatus has a processing space provided with a holding stand for holding a substrate to be processed. A hydrogen catalyzing member is arranged in the processing space to face the substrate and for decomposing hydrogen molecules into hydrogen radicals H*. A gas feeding port is arranged in the processing space on an opposite side of the hydrogen catalyzing member to the substrate for feeding a processing gas including at least hydrogen gas. An interval between the hydrogen catalyzing member and the substrate on the holding stand is set less than the distance that the hydrogen radicals H* can reach.
摘要翻译：衬底处理设备具有设置有用于保持待处理衬底的保持架的处理空间。在处理空间中配置氢气催化构件以面对衬底并将氢分子分解成氢原子H *。气体供给口设置在处理空间中，在与氢气催化构件相对的基板上，供给至少包含氢气的处理气体。氢催化构件和保持架上的基板之间的间隔被设定为小于氢根H *可以达到的距离。

62. 发明授权

US07424595B2 System for managing circuitry of variable function information processing circuit and method for managing circuitry of variable function information processing circuit 失效
标题翻译：用于管理可变功能信息处理电路的电路的系统和用于管理可变功能信息处理电路的电路的方法
公开(公告)号：US07424595B2
公开(公告)日：2008-09-09
申请号：US10296640
申请日：2001-06-06
申请人： Tadahiro Ohmi , Tatsuo Morimoto , Akira Nakada , Shigetoshi Sugawa
发明人： Tadahiro Ohmi , Tatsuo Morimoto , Akira Nakada , Shigetoshi Sugawa
IPC分类号： G06F15/17 , G06F9/54
CPC分类号： G06F9/44505 , G06F9/3897
摘要： Configuration management information having circuit configuration information for altering a circuit configuration of an FPGA (12) is stored in a memory (13), the configuration management information according to information related to an instruction group, which is supplied by a configuration management unit (11) from the outside via a signal line group (14), is read from the memory (13), and the circuit configuration of the FPGA (12) is altered according to the read configuration management information to execute processing of the instruction group so that information processing by software is replaced by information processing by hardware in real time, which increases execution speed of information processing and shortens verification time of software, enabling software development in a shorter period and with higher efficiency.
摘要翻译：具有用于改变FPGA（12）的电路配置的电路配置信息的配置管理信息被存储在存储器（13）中，根据由配置管理单元（11）提供的与指令组相关的信息，）经由信号线组（14）从存储器（13）读取，并且根据读取的配置管理信息改变FPGA（12）的电路配置，以执行指令组的处理，使得软件信息处理由硬件实时信息处理取代，提高了信息处理的执行速度，缩短了软件验证时间，使软件开发更短，效率更高。

63. 发明申请

US20060278909A1 Mis transistor and cmos transistor 审中-公开
标题翻译：误差晶体管和cmos晶体管
公开(公告)号：US20060278909A1
公开(公告)日：2006-12-14
申请号：US10560706
申请日：2004-06-11
申请人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： H01L29/94
CPC分类号： H01L29/7851 , H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L29/045
摘要： A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate (702, 910) comprising a projecting part (704, 910B) with at least two different crystal planes on the surface on a principal plane, a gate insulator (708, 920B) for covering at least a part of each of said at least two different crystal planes constituting the surface of the projecting part, a gate electrode (706, 930B), comprised on each of said at least two different crystal planes constituting the surface of the projecting part, which sandwiches the gate insulator with the said at least two different planes, and a single conductivity type diffusion region (710a, 710b, 910c, 910d) formed in the projecting part facing each of said at least two different crystal planes and individually formed on both sides of the gate electrode. Such a configuration allows control over increase in the element area and increase of channel width.
摘要翻译：形成在半导体衬底上的MIS晶体管被认为包括半导体衬底（702,910），该半导体衬底包括在主平面上的表面上具有至少两个不同晶面的突出部分（704,910B），栅极绝缘体 708,920B），用于覆盖构成突出部分的表面的所述至少两个不同晶面的每一个的至少一部分;栅电极（706,930B），包括在所述至少两个不同晶面中的每一个上构成突出部分的表面，其将栅极绝缘体与所述至少两个不同的平面夹住，并且形成在突出部分中的单个导电型扩散区域（710a，710b，910c，910d）所述至少两个不同的晶面并且分别形成在所述栅电极的两侧。这种配置允许控制元件面积的增加和通道宽度的增加。

64. 发明申请

US20060261037A1 Substrate processing method and substrate processing apparatus 审中-公开
标题翻译：基板处理方法和基板处理装置
公开(公告)号：US20060261037A1
公开(公告)日：2006-11-23
申请号：US11496440
申请日：2006-08-01
申请人： Tadahiro Ohmi , Shigetoshi Sugawa , Masaki Hirayama
发明人： Tadahiro Ohmi , Shigetoshi Sugawa , Masaki Hirayama
IPC分类号： C23F1/00 , H01L21/302 , H01L21/306 , C03C25/68
CPC分类号： H01L21/02247 , C23C8/36 , H01J37/321 , H01J37/32357 , H01L21/02252 , H01L21/3143 , H01L21/318
摘要： In a substrate processing apparatus, a control electrode (131) separates a process space (11C) including a substrate to be processed and a plasma formation space (11B) not including the substrate. The control electrode includes a conductive member formed in a processing vessel and having a plurality of apertures (131a) for passing plasma. A surface of the control electrode is covered by an aluminum oxide or a conductive nitride. In the substrate processing apparatus, a gas containing He and N2 is supplied into the processing vessel. In the plasma formation space, there is formed plasma under a condition in which atomic state nitrogen N* are excited. The atomic state nitrogen N* are used to nitride a surface of the substrate.
摘要翻译：在衬底处理装置中，控制电极（131）分离包括待处理衬底和不包括衬底的等离子体形成空间（11B）的处理空间（11C）。控制电极包括形成在处理容器中并具有用于使等离子体通过的多个孔（131a）的导电构件。控制电极的表面被氧化铝或导电氮化物覆盖。在基板处理装置中，将含有He和N 2的气体供给到处理容器中。在等离子体形成空间中，在原子态氮N *被激发的条件下形成等离子体。原子态氮N *用于氮化衬底的表面。

65. 发明申请

US20060252160A1 Electron beam exposure device and exposure method 审中-公开
标题翻译：电子束曝光装置和曝光方法
公开(公告)号：US20060252160A1
公开(公告)日：2006-11-09
申请号：US10567828
申请日：2004-08-09
申请人： Tadahiro Ohmi , Shigetoshi Sugawa , Kimio Yanagida , Kiwamu Takehisa
发明人： Tadahiro Ohmi , Shigetoshi Sugawa , Kimio Yanagida , Kiwamu Takehisa
IPC分类号： C23C16/00 , H01L21/00
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/20 , H01J37/3174
摘要： A 1:1 mask and a wafer are arranged so as to be vertical. Thus, a pattern portion of the 1:1 mask does not warp at all and, therefore, even when the mask has no beam, it is not necessary to strongly stretch a pattern portion thereof. Further, a gap between the mask and the wafer can be further reduced. Since it is not necessary to strongly stretch the pattern portion of the stencil mask, a very thin membrane can be bonded to the pattern portion. Thus, even when the acceleration voltage of an electron beam is as low as several kV, it is possible to use a mask called a membrane mask and carry out pattern formation by one-time exposure even in the case of a doughnut-shaped pattern.
摘要翻译： 1：1掩模和晶片布置成垂直。因此，1：1掩模的图案部分根本不翘曲，因此即使当掩模没有光束时，也不需要强烈地拉伸图案部分。此外，可以进一步减小掩模和晶片之间的间隙。由于不需要强力地拉伸模板掩模的图案部分，所以可以将非常薄的膜结合到图案部分。因此，即使当电子束的加速电压低至几kV时，也可以使用称为膜掩模的掩模，并且即使在环形图案的情况下也可以通过一次曝光进行图案形成。

66. 发明申请

US20060138476A1 Dc amplifier and semiconductor integrated circuit therefor 审中-公开
标题翻译： Dc放大器及其半导体集成电路
公开(公告)号：US20060138476A1
公开(公告)日：2006-06-29
申请号：US10560704
申请日：2004-06-11
申请人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： H01L29/76
CPC分类号： H01L29/7851 , H01L21/823807 , H01L21/82385 , H01L27/092 , H01L29/66795 , H03F3/343 , H03F3/45183 , H03F2200/372
摘要： A rectangular parallelepiped projecting portion 21 having a height of HB and a width of WB is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the projecting portion 21. A source and a drain are formed on both sides of the gate electrode 26 to form a MOS transistor. The MOS transistor configures a DC amplifier. The DC amplifier includes a differential amplification circuit having MOS transistors 61 and 62, thereby realizing a high-gain DC amplifier.
摘要翻译：在硅衬底上形成具有H B B高度和W B B的宽度的长方体的突出部分21，并且栅极氧化膜形成在突出部分21的顶表面和侧表面。源极和漏极形成在栅电极26的两侧以形成MOS晶体管。 MOS晶体管配置一个直流放大器。 DC放大器包括具有MOS晶体管61和62的差分放大电路，从而实现高增益DC放大器。

67. 发明申请

US20060131553A1 Silicon semiconductor substrate and its manufacturing method 有权
标题翻译：硅半导体衬底及其制造方法
公开(公告)号：US20060131553A1
公开(公告)日：2006-06-22
申请号：US10543166
申请日：2004-01-29
申请人： Hideki Yamanaka , Kiyoshi Demizu , Tadahiro Ohmi , Akinobu Teramoto , Shigetoshi Sugawa
发明人： Hideki Yamanaka , Kiyoshi Demizu , Tadahiro Ohmi , Akinobu Teramoto , Shigetoshi Sugawa
IPC分类号： H01L47/00
CPC分类号： H01L21/28167 , H01L21/02008 , H01L21/02027 , H01L21/02381 , H01L21/02428 , H01L21/02433 , H01L21/02532 , H01L21/02658 , H01L29/045
摘要： The present invention has been made in order to manufacture a silicon semiconductor substrate used for a semiconductor integrated circuit device, higher in carrier mobility, especially in electron mobility, which is a carrier of an n-type FET, on a {100} plane as a main surface, and provides a silicon semiconductor substrate and a method for manufacturing the same, wherein the conventional RCA cleaning is employed without the use of special cleaning and the surface of the substrate is planarized at an atomic level to thereby decrease the surface roughness thereof without the use of the radical oxidation. The present invention provides a silicon semiconductor substrate comprising: a {110} plane or a plane inclined from a {110} plane as a main surface of the substrate; and steps arranged at an atomic level along a orientation on the main surface.
摘要翻译：本发明是为了制造用于半导体集成电路器件的硅半导体衬底，在{100}面作为载流子迁移率，尤其是作为n型FET的载流子的电子迁移率中，作为主表面，并提供硅半导体衬底及其制造方法，其中采用常规的RCA清洗而不使用特殊的清洁，并且基板的表面在原子级平坦化，从而降低其表面粗糙度而不使用自由基氧化。本发明提供了一种硅半导体衬底，其包括：{110}面或从{110}面倾斜作为衬底的主表面的平面; 以及沿着主表面沿<110>方向布置在原子水平的台阶。

68. 发明授权

US07026681B2 Flash memory device and fabrication process thereof, method of forming a dielectric film 有权
公开(公告)号：US07026681B2
公开(公告)日：2006-04-11
申请号：US10359592
申请日：2003-02-07
申请人： Tadahiro Ohmi , Shigetoshi Sugawa
发明人： Tadahiro Ohmi , Shigetoshi Sugawa
IPC分类号： H01L29/76
CPC分类号： H01L21/31641 , C23C8/02 , C23C8/36 , H01L21/0217 , H01L21/02238 , H01L21/02247 , H01L21/02252 , H01L21/02323 , H01L21/02329 , H01L21/0234 , H01L21/3105 , H01L21/3144 , H01L21/31612 , H01L21/31637 , H01L21/31662 , H01L21/3185 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42324
摘要： A fabrication process of a flash memory device includes microwave excitation of high-density plasma in a mixed gas of Kr and an oxidizing gas or a nitriding gas. The resultant atomic state oxygen O* or hydrogen nitride radicals NH* are used for nitridation or oxidation of a polysilicon electrode surface. It is also disclosed the method of forming an oxide film and a nitride film on a polysilicon film according to such a plasma processing.

69. 发明授权

US07001855B2 Flash memory device and fabrication process thereof, method of forming a dielectric film 失效
公开(公告)号：US07001855B2
公开(公告)日：2006-02-21
申请号：US10359701
申请日：2003-02-07
申请人： Tadahiro Ohmi , Shigetoshi Sugawa
发明人： Tadahiro Ohmi , Shigetoshi Sugawa
IPC分类号： H01L21/31
CPC分类号： H01L21/31641 , C23C8/02 , C23C8/36 , H01L21/0217 , H01L21/02238 , H01L21/02247 , H01L21/02252 , H01L21/02323 , H01L21/02329 , H01L21/0234 , H01L21/3105 , H01L21/3144 , H01L21/31612 , H01L21/31637 , H01L21/31662 , H01L21/3185 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42324
摘要： A fabrication process of a flash memory device includes microwave excitation of high-density plasma in a mixed gas of Kr and an oxidizing gas or a nitriding gas. The resultant atomic state oxygen O* or hydrogen nitride radicals NH* are used for nitridation or oxidation of a polysilicon electrode surface. It is also disclosed the method of forming an oxide film and a nitride film on a polysilicon film according to such a plasma processing.

70. 发明授权

US06998355B2 Flash memory device and a fabrication process thereof, method of forming a dielectric film 有权
公开(公告)号：US06998355B2
公开(公告)日：2006-02-14
申请号：US10762520
申请日：2004-01-23
申请人： Tadahiro Ohmi , Shigetoshi Sugawa
发明人： Tadahiro Ohmi , Shigetoshi Sugawa
IPC分类号： H01L21/31
CPC分类号： H01L21/31641 , C23C8/02 , C23C8/36 , H01L21/0217 , H01L21/02238 , H01L21/02247 , H01L21/02252 , H01L21/02323 , H01L21/02329 , H01L21/0234 , H01L21/3105 , H01L21/3144 , H01L21/31612 , H01L21/31637 , H01L21/31662 , H01L21/3185 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42324
摘要： A fabrication process of a flash memory device includes microwave excitation of high-density plasma in a mixed gas of Kr and an oxidizing gas or a nitriding gas. The resultant atomic state oxygen O* or hydrogen nitride radicals NH* are used for nitridation or oxidation of a polysilicon electrode surface. It is also disclosed the method of forming an oxide film and a nitride film on a polysilicon film according to such a plasma processing.

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