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1. 发明申请

US20070105523A1 Low noise amplifier 审中-公开
标题翻译：低噪声放大器
公开(公告)号：US20070105523A1
公开(公告)日：2007-05-10
申请号：US10560703
申请日：2004-06-11
申请人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： H04B1/10 , H04B1/28 , H04B1/16
CPC分类号： H01L21/82385 , H01L21/823807 , H01L27/092 , H01L29/785 , H03F1/26 , H03F2200/372 , H03G1/0029 , H03G1/007
摘要： A low noise amplifier is assumed to comprise an MIS transistor and to amplify an input signal keeping noise at a low level, and the MIS transistor comprises a semiconductor substrate for comprising a first crystal plane as a principal plane, a semiconductor structure, formed as a part of the semiconductor substrate, for comprising a pair of sidewall planes defined by the second crystal plane different from the first crystal plane and a top plane defined by the third crystal plane different from the second crystal plane, a gate insulator of uniform thickness covering the principal plane, the sidewall planes and the top plane, a gate electrode for continuously covering the principal plane, the sidewall planes and the top plane on top of the gate insulator, and a single conductivity type diffusion area formed in the region to either side of the gate electrode in the semiconductor substrate and the semiconductor structure and continuously extending along the principal plane, the sidewall planes and the top plane. Such a configuration allows significant reduction of the 1/f noise and the signal distortion applied to an output signal by the low noise amplifier and therefore a circuit for compensating for the reduction of the amplitude is no longer of necessity, allowing reduction in size.
摘要翻译：假设低噪声放大器包括MIS晶体管并且将保持噪声保持在低电平的输入信号放大，并且MIS晶体管包括用于包括第一晶面作为主平面的半导体衬底，形成为所述半导体衬底的一部分包括由不同于所述第一晶体面的所述第二晶体面限定的一对侧壁平面和由与所述第二晶体面不同的所述第三晶体面限定的顶面，覆盖所述半导体衬底的均匀厚度的栅极绝缘体主平面，侧壁平面和顶面，用于连续覆盖主平面，侧壁平面和栅极绝缘体顶部的顶面的栅极，以及在该区域中形成的单一导电型扩散区域半导体衬底中的栅电极和半导体结构，并且沿着主平面连续延伸，侧壁p 车道和顶层飞机。这样的配置允许显着降低由低噪声放大器施加到输出信号的1 / f噪声和信号失真，因此不再需要用于补偿幅度减小的电路，从而允许尺寸减小。

2. 发明申请

US20060180840A1 Switched capacitor circuit and semiconductor integrated circuit thereof 审中-公开
标题翻译：开关电容电路及其半导体集成电路
公开(公告)号：US20060180840A1
公开(公告)日：2006-08-17
申请号：US10560397
申请日：2004-06-11
申请人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/66787 , H01L21/823807 , H01L21/82385 , H01L27/092
摘要： A rectangular parallelepiped projecting portion (21) having a height of HB and a width of WB is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the projecting portion (21), thereby generating a MOS transistor. By connecting in parallel a p-channel MOS transistor and an n-channel MOS transistor produced as described above, a switch of a switched capacitor circuit is configured, thereby reducing a leak current and a DC offset of the switched capacitor circuit.
摘要翻译：在硅衬底上形成具有H B高度和W B B的宽度的长方体的突出部分（21），并且栅极氧化膜形成在突出部分（21）的顶表面和侧表面的一部分，从而产生MOS晶体管。通过并联连接如上所述制造的p沟道MOS晶体管和n沟道MOS晶体管，构造开关电容器电路的开关，从而减小开关电容器电路的漏电流和DC偏移。

3. 发明申请

US20060278909A1 Mis transistor and cmos transistor 审中-公开
标题翻译：误差晶体管和cmos晶体管
公开(公告)号：US20060278909A1
公开(公告)日：2006-12-14
申请号：US10560706
申请日：2004-06-11
申请人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： H01L29/94
CPC分类号： H01L29/7851 , H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L29/045
摘要： A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate (702, 910) comprising a projecting part (704, 910B) with at least two different crystal planes on the surface on a principal plane, a gate insulator (708, 920B) for covering at least a part of each of said at least two different crystal planes constituting the surface of the projecting part, a gate electrode (706, 930B), comprised on each of said at least two different crystal planes constituting the surface of the projecting part, which sandwiches the gate insulator with the said at least two different planes, and a single conductivity type diffusion region (710a, 710b, 910c, 910d) formed in the projecting part facing each of said at least two different crystal planes and individually formed on both sides of the gate electrode. Such a configuration allows control over increase in the element area and increase of channel width.
摘要翻译：形成在半导体衬底上的MIS晶体管被认为包括半导体衬底（702,910），该半导体衬底包括在主平面上的表面上具有至少两个不同晶面的突出部分（704,910B），栅极绝缘体 708,920B），用于覆盖构成突出部分的表面的所述至少两个不同晶面的每一个的至少一部分;栅电极（706,930B），包括在所述至少两个不同晶面中的每一个上构成突出部分的表面，其将栅极绝缘体与所述至少两个不同的平面夹住，并且形成在突出部分中的单个导电型扩散区域（710a，710b，910c，910d）所述至少两个不同的晶面并且分别形成在所述栅电极的两侧。这种配置允许控制元件面积的增加和通道宽度的增加。

4. 发明申请

US20060138476A1 Dc amplifier and semiconductor integrated circuit therefor 审中-公开
标题翻译： Dc放大器及其半导体集成电路
公开(公告)号：US20060138476A1
公开(公告)日：2006-06-29
申请号：US10560704
申请日：2004-06-11
申请人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： H01L29/76
CPC分类号： H01L29/7851 , H01L21/823807 , H01L21/82385 , H01L27/092 , H01L29/66795 , H03F3/343 , H03F3/45183 , H03F2200/372
摘要： A rectangular parallelepiped projecting portion 21 having a height of HB and a width of WB is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the projecting portion 21. A source and a drain are formed on both sides of the gate electrode 26 to form a MOS transistor. The MOS transistor configures a DC amplifier. The DC amplifier includes a differential amplification circuit having MOS transistors 61 and 62, thereby realizing a high-gain DC amplifier.
摘要翻译：在硅衬底上形成具有H B B高度和W B B的宽度的长方体的突出部分21，并且栅极氧化膜形成在突出部分21的顶表面和侧表面。源极和漏极形成在栅电极26的两侧以形成MOS晶体管。 MOS晶体管配置一个直流放大器。 DC放大器包括具有MOS晶体管61和62的差分放大电路，从而实现高增益DC放大器。

5. 发明授权

US08314449B2 MIS transistor and CMOS transistor 有权
标题翻译： MIS晶体管和CMOS晶体管
公开(公告)号：US08314449B2
公开(公告)日：2012-11-20
申请号：US12604015
申请日：2009-10-22
申请人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： H01L21/76
CPC分类号： H01L29/7851 , H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L29/045
摘要： A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate (702, 910) comprising a projecting part (704, 910B) with at least two different crystal planes on the surface on a principal plane, a gate insulator (708, 920B) for covering at least a part of each of said at least two different crystal planes constituting the surface of the projecting part, a gate electrode (706, 930B), comprised on each of said at least two different crystal planes constituting the surface of the projecting part, which sandwiches the gate insulator with the said at least two different planes, and a single conductivity type diffusion region (710a, 710b, 910c, 910d) formed in the projecting part facing each of said at least two different crystal planes and individually formed on both sides of the gate electrode. Such a configuration allows control over increase in the element area and increase of channel width.
摘要翻译：形成在半导体衬底上的MIS晶体管被假设为包括半导体衬底（702,910），该半导体衬底包括在主平面上的表面上具有至少两个不同晶面的突出部分（704,910B），栅极绝缘体（708 ，920B），用于覆盖构成所述突出部分的表面的所述至少两个不同晶面的每一个的至少一部分;栅电极（706,930B），包括在构成所述表面的所述至少两个不同晶面中的每一个上所述突出部分与所述至少两个不同平面夹住所述栅极绝缘体，以及形成在所述突出部分中的所述至少两个不同晶面中的每一个的单导电型扩散区域（710a，710b，910c，910d）并分别形成在栅电极的两侧。这种配置允许控制元件面积的增加和通道宽度的增加。

6. 发明申请

US20070142017A1 Mixer circuit 审中-公开
标题翻译：搅拌机电路
公开(公告)号：US20070142017A1
公开(公告)日：2007-06-21
申请号：US10560398
申请日：2004-06-11
申请人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： H04B1/26 , H04B1/28
CPC分类号： H01L29/1033 , H01L21/823807 , H01L21/82385 , H01L29/045 , H03D7/1441 , H03D7/1458 , H03D2200/0033 , H03D2200/0047
摘要： A mixer circuit is configured using a CMOS transistor (800), comprising a p-channel transistor (840A) and an n-channel transistor (840B) in which semiconductor substrates (810A, 810) with at least two crystal planes and a gate insulator (820A) formed on at least two of the crystal planes on the semiconductor substrate are comprised and the channel width of a channel formed in the semiconductor substrate along with the gate insulator is represented by summation of each of the channel widths of channels individually formed on said at least two crystal planes. Such a configuration allows reduction of 1/f noise, DC offset generated in output signals due to variation in electrical characteristics of a transistor element, and signal distortion based on the channel length modulation effect.
摘要翻译：使用CMOS晶体管（800）构成混频器电路，其包括p沟道晶体管（840A）和n沟道晶体管（840B），其中具有至少两个晶体面的半导体衬底（810A，810）和包括形成在半导体衬底上的至少两个晶面上的栅极绝缘体（820A），并且与栅极绝缘体一起形成在半导体衬底中的沟道的沟道宽度由每个沟道宽度的和在所述至少两个晶面上分别形成的通道。这样的配置允许减少由于晶体管元件的电特性的变化而在输出信号中产生的1 / f噪声，DC偏移以及基于沟道长度调制效应的信号失真。

7. 发明申请

US20060139821A1 Limiter circuit and semiconductor integrated circuit thereof 审中-公开
标题翻译：限幅电路及其半导体集成电路
公开(公告)号：US20060139821A1
公开(公告)日：2006-06-29
申请号：US10560646
申请日：2004-06-11
申请人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： H02H9/00
CPC分类号： H03G1/0029 , H01L21/823807 , H01L21/82385 , H01L27/092 , H01L29/66795 , H03G1/0023 , H03G7/00 , H03K5/08
摘要： A rectangular parallelepiped p-channel MOS transistor 21 having a height of HB and a width of WB is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the p-channel MOS transistor 21. A source and a drain are formed on both sides of a gate electrode 26 to form a MOS transistor. A differential amplification circuit including MOS transistors 61 and 62 configures a limiter circuit. Thus, the gain of the limiter circuit can be designed large.
摘要翻译：在硅衬底上形成具有H B高度和W B B的高度的长方体p沟道MOS晶体管21，并且在 p沟道MOS晶体管21的顶表面和侧表面的一部分。源极和漏极形成在栅电极26的两侧以形成MOS晶体管。包括MOS晶体管61和62的差分放大电路配置限幅器电路。因此，限制电路的增益可以设计得很大。

8. 发明授权

US08183670B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08183670B2
公开(公告)日：2012-05-22
申请号：US11651034
申请日：2007-01-09
申请人： Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto , Hiroshi Akahori , Keiichi Nii
发明人： Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto , Hiroshi Akahori , Keiichi Nii
IPC分类号： H01L29/04
CPC分类号： H01L21/3185 , H01L21/30604 , H01L21/31654 , H01L21/318 , H01L29/6659
摘要： In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.
摘要翻译：在形成在具有大致（110）晶面取向的硅表面上的半导体器件中，硅表面变平，使得表面Ra的算术平均偏差不大于0.15nm，优选为0.09nm，这使得能够制造高迁移率的n-MOS晶体管。通过在脱氧H 2 O或低OH密度气氛中清洗硅表面，通过在氧自由基气氛中重复自牺牲氧化物膜的沉积工艺和自牺牲氧化物膜的去除工艺来获得这种扁平化的硅表面，或通过氢或重氢强烈地终止硅表面。自牺牲氧化膜的沉积工艺可以通过各向同性氧化进行。

9. 发明申请

US20110110052A1 MULTILAYER WIRING BOARD 有权
标题翻译：多层接线板
公开(公告)号：US20110110052A1
公开(公告)日：2011-05-12
申请号：US12995514
申请日：2009-05-22
申请人： Tadahiro Ohmi , Shigetoshi Sugawa , Hiroshi Imai , Akinobu Teramoto
发明人： Tadahiro Ohmi , Shigetoshi Sugawa , Hiroshi Imai , Akinobu Teramoto
IPC分类号： H05K1/18 , H05K1/00
CPC分类号： H05K1/0218 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2223/6688 , H01L2924/0002 , H01L2924/19032 , H01L2924/3011 , H05K1/025 , H05K1/0265 , H05K3/4652 , H05K2201/0191 , H05K2201/0352 , H05K2201/0715 , H05K2201/096 , H05K2201/09618 , H05K2201/09727 , H05K2201/09972 , H01L2924/00
摘要： A multilayer wiring board 100 comprises a first wiring region 101 where wirings 103a and insulating layers 104a and 104b are alternately laminated, and a second wiring region 102 where a thickness H2 of an insulating layer 104 is twice or more a thickness H1 of the insulating layer in the first wiring region 101 and a width W2 of a wiring 103b is twice or more a width W1 of the wiring in the first wiring region 101. The first wiring region 101 and the second wiring region 102 are integrally formed on the same board.
摘要翻译：多层布线基板100包括：布线103a和绝缘层104a，104b交替层叠的第一布线区域101和绝缘层104的厚度H2为绝缘层的厚度H1的两倍以上的第二布线区域102 在第一布线区域101中，布线103b的宽度W2是第一布线区域101中的布线的宽度W1的两倍或更多倍。第一布线区域101和第二布线区域102一体地形成在同一个板上。

10. 发明授权

US08633395B2 Multilayer wiring board 有权
标题翻译：多层接线板
公开(公告)号：US08633395B2
公开(公告)日：2014-01-21
申请号：US12995514
申请日：2009-05-22
申请人： Tadahiro Ohmi , Shigetoshi Sugawa , Hiroshi Imai , Akinobu Teramoto
发明人： Tadahiro Ohmi , Shigetoshi Sugawa , Hiroshi Imai , Akinobu Teramoto
IPC分类号： H05K1/03 , H05K1/11
CPC分类号： H05K1/0218 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2223/6688 , H01L2924/0002 , H01L2924/19032 , H01L2924/3011 , H05K1/025 , H05K1/0265 , H05K3/4652 , H05K2201/0191 , H05K2201/0352 , H05K2201/0715 , H05K2201/096 , H05K2201/09618 , H05K2201/09727 , H05K2201/09972 , H01L2924/00
摘要： A multilayer wiring board 100 comprises a first wiring region 101 where wirings 103a and insulating layers 104a and 104b are alternately laminated, and a second wiring region 102 where a thickness H2 of an insulating layer 104 is twice or more a thickness H1 of the insulating layer in the first wiring region 101 and a width W2 of a wiring 103b is twice or more a width W1 of the wiring in the first wiring region 101. The first wiring region 101 and the second wiring region 102 are integrally formed on the same board.
摘要翻译：多层布线基板100包括：布线103a和绝缘层104a，104b交替层叠的第一布线区域101和绝缘层104的厚度H2为绝缘层的厚度H1的两倍以上的第二布线区域102 在第一布线区域101中，布线103b的宽度W2是第一布线区域101中的布线的宽度W1的两倍或更多倍。第一布线区域101和第二布线区域102一体地形成在同一个板上。

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