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61. 发明申请

US20120001268A1 ISOLATION WITH OFFSET DEEP WELL IMPLANTS 审中-公开
标题翻译：隔离深度较深的植入物
公开(公告)号：US20120001268A1
公开(公告)日：2012-01-05
申请号：US13228998
申请日：2011-09-09
申请人： James W. Adkisson , Andres Bryant , Mark D. Jaffe , Alain Loiseau
发明人： James W. Adkisson , Andres Bryant , Mark D. Jaffe , Alain Loiseau
IPC分类号： H01L27/092
CPC分类号： H01L29/1083 , H01L21/26513 , H01L21/823892
摘要： A method implants impurities into well regions of transistors. The method prepares a first mask over a substrate and performs a first shallow well implant through the first mask to implant first-type impurities to a first depth of the substrate. The first mask is removed and a second mask is prepared over the substrate. The method performs a second shallow well implant through the second mask to implant second-type impurities to the first depth of the substrate and then removes the second mask. A third mask is prepared over the substrate. The third mask has openings smaller than openings in the first mask and the second mask. A first deep well implant is performed through the third mask to implant the first-type impurities to a second depth of the substrate, the second depth of the substrate being greater than the first depth of the substrate. The third mask is removed and a fourth mask is prepared over the substrate, the fourth mask has openings smaller than the openings in the first mask and the second mask. Then, a second deep well implant is performed through the fourth mask to implant the second-type impurities to the second depth of the substrate.
摘要翻译：一种方法是将杂质掺入晶体管的阱区。该方法在衬底上制备第一掩模，并且通过第一掩模执行第一浅阱注入，以将第一类型的杂质注入衬底的第一深度。去除第一个掩模，并在衬底上制备第二个掩模。该方法通过第二掩模执行第二浅井注入，以将第二类型杂质植入衬底的第一深度，然后移除第二掩模。在衬底上制备第三个掩模。第三掩模具有比第一掩模和第二掩模中的开口小的开口。通过第三掩模执行第一深孔注入，以将第一类型的杂质注入衬底的第二深度，衬底的第二深度大于衬底的第一深度。去除第三掩模并在衬底上制备第四掩模，第四掩模具有小于第一掩模和第二掩模中的开口的开口。然后，通过第四掩模进行第二深孔注入，以将第二类型的杂质植入到衬底的第二深度。

62. 发明申请

US20110250715A1 METHODS FOR FORMING ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS 有权
标题翻译：用于形成CMOS图像传感器的抗反射结构的方法
公开(公告)号：US20110250715A1
公开(公告)日：2011-10-13
申请号：US13165375
申请日：2011-06-21
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
IPC分类号： H01L31/02 , H01L21/56
CPC分类号： H01L27/14685 , H01L27/14618 , H01L27/14625 , H01L27/14627 , H01L27/14632 , H01L27/14645 , H01L27/14689 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sublithographic features of a first polymeric block component within a matrix of a second polymeric block component. The pattern of the polymeric block component is transferred into a first optical layer to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.
摘要翻译：在具有不同折射率的两层之间的光学界面处形成具有小于由光电二极管可检测的光的波长范围的垂直和横向尺寸的突起。突起可以通过采用在第二聚合物嵌段组分的基质内形成第一聚合物嵌段组分的亚光刻特征阵列的自组装嵌段共聚物来形成。聚合物嵌段组分的图案被转移到第一光学层中以形成纳米级突起的阵列。或者，可以使用常规光刻来形成尺寸小于光的波长的突起。第二光学层直接形成在第一光学层的突起上。第一和第二光学层之间的界面具有渐变的折射率，并提供很少的反射光的高透射率。

63. 发明授权

US08023021B2 High efficiency CMOS image sensor pixel employing dynamic voltage supply 失效
标题翻译：采用动态电压源的高效率CMOS图像传感器像素
公开(公告)号：US08023021B2
公开(公告)日：2011-09-20
申请号：US12641589
申请日：2009-12-18
申请人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Charles F. Musante , Richard J. Rassel
发明人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Charles F. Musante , Richard J. Rassel
IPC分类号： H04N5/335
CPC分类号： H04N5/361 , G06F17/5063 , H04N5/359 , H04N5/3745
摘要： A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.
摘要翻译：提供了包括复位栅极（RG）晶体管的全局快门兼容像素电路，其中动态电压被施加到复位栅极晶体管的漏极，以便减少在信号保持时间期间通过其的浮动扩散（FD）泄漏。复位栅极晶体管的漏极电压保持在比电路电源电压更低的电压，以最小化通过RG晶体管的截止状态泄漏，从而减少信号保持时间期间浮动扩散时的电压变化。此外，还提供了用于向像素电路的复位栅极的漏极提供动态电压的这种电路的设计结构。

64. 发明申请

US20110008925A1 CMOS IMAGE SENSOR WITH REDUCED DARK CURRENT 有权
标题翻译： CMOS图像传感器具有降低的电流
公开(公告)号：US20110008925A1
公开(公告)日：2011-01-13
申请号：US12885648
申请日：2010-09-20
申请人： James W. Adkisson , Rajendran Krishnasamy
发明人： James W. Adkisson , Rajendran Krishnasamy
IPC分类号： H01L31/18
CPC分类号： H01L27/14603
摘要： A carbon-containing semiconductor layer is formed on exposed surfaces of a p− doped semiconductor layer abutting sidewalls of a shallow trench. Following formation of a dielectric layer on the carbon-containing semiconductor layer, a surface pinning layer having a p-type doping is formed underneath the carbon-containing semiconductor layer. A shallow trench isolation structure and a photodiode are subsequently formed. Diffusion of defects directly beneath the shallow trench isolation structure, now contained in the carbon-containing semiconductor layer, is suppressed. Further, boron diffusion into the shallow trench isolation structure and into the photodiode is also suppressed by the carbon-containing semiconductor layer, providing reduction in dark current and enhancement of performance of the photodiode.
摘要翻译：在邻接浅沟槽的侧壁的p掺杂半导体层的暴露表面上形成含碳半导体层。在含碳半导体层上形成电介质层之后，在含碳半导体层的下面形成具有p型掺杂的表面钉扎层。随后形成浅沟槽隔离结构和光电二极管。现在包含在含碳半导体层中的浅沟槽隔离结构正下方的缺陷的扩散被抑制。此外，通过含碳半导体层也抑制了进入浅沟槽隔离结构并进入光电二极管的硼，从而提供了暗电流的降低和光电二极管的性能的提高。

65. 发明授权

US07829945B2 Lateral diffusion field effect transistor with asymmetric gate dielectric profile 有权
标题翻译：具有不对称栅极电介质轮廓的侧向扩散场效应晶体管
公开(公告)号：US07829945B2
公开(公告)日：2010-11-09
申请号：US11924650
申请日：2007-10-26
申请人： James W. Adkisson , Natalie B. Feilchenfeld , Jeffrey P. Gambino , Benjamin T. Voegeli , Michael J. Zierak
发明人： James W. Adkisson , Natalie B. Feilchenfeld , Jeffrey P. Gambino , Benjamin T. Voegeli , Michael J. Zierak
IPC分类号： H01L21/331
CPC分类号： H01L29/7835 , H01L29/1045 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/512 , H01L29/66659
摘要： A gate stack comprising a uniform thickness gate dielectric, a gate electrode, and an oxygen-diffusion-resistant gate cap is formed on a semiconductor substrate. Thermal oxidation is performed only on the drain side of the gate electrode, while the source side is protected from thermal oxidation. A thermal oxide on the drain side sidewall of the gate electrode is integrally formed with a graded thickness silicon oxide containing gate dielectric, of which the thickness monotonically increases from the source side to the drain side. The thickness profile may be self-aligned to the drain side edge of the gate electrode, or may have a portion with a self-limiting thickness. The graded thickness profile may be advantageously used to form a lateral diffusion metal oxide semiconductor field effect transistor providing an enhanced performance.
摘要翻译：在半导体基板上形成包括均匀厚度的栅极电介质，栅电极和耐氧扩散栅极盖的栅极堆叠。仅在栅电极的漏极侧进行热氧化，同时防止源极侧受热氧化。栅电极的漏极侧壁上的热氧化物与层状厚度的含氧化硅的栅极电介质整体形成，其厚度从源极侧向漏极侧单调增加。厚度分布可以与栅电极的漏极侧边缘自对准，或者可以具有自限制厚度的部分。梯度厚度分布可以有利地用于形成提供增强性能的横向扩散金属氧化物半导体场效应晶体管。

66. 发明申请

US20100264473A1 ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS 有权
标题翻译： CMOS图像传感器的抗反射结构
公开(公告)号：US20100264473A1
公开(公告)日：2010-10-21
申请号：US12770349
申请日：2010-04-29
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
IPC分类号： H01L31/0232 , H01L31/0203 , H01L31/02
CPC分类号： H01L31/103 , H01L24/05 , H01L24/73 , H01L27/14603 , H01L27/1462 , H01L27/14627 , H01L27/14629 , H01L27/1464 , H01L27/14643 , H01L31/02165 , H01L31/0236 , H01L2224/04042 , H01L2224/05 , H01L2224/32225 , H01L2224/48227 , H01L2224/48464 , H01L2224/4847 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/12043 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/3025 , Y02E10/50 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.
摘要翻译：提供了具有不同折射率的两层之间的突起阵列的光学结构。突起阵列具有小于由CMOS图像传感器的光电二极管可检测的光的波长范围的垂直和侧向尺寸。突起的阵列提供了很少的反射光的高透射率。突起阵列可以设置在光电二极管上，后端行互连结构中，用于光电二极管的透镜，光电二极管的背面或芯片封装的窗口上。

67. 发明授权

US07781781B2 CMOS imager array with recessed dielectric 有权
标题翻译：具有凹陷电介质的CMOS成像器阵列
公开(公告)号：US07781781B2
公开(公告)日：2010-08-24
申请号：US11560882
申请日：2006-11-17
申请人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L27/15
CPC分类号： H01L27/14687 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L27/14685 , H01L2224/05001 , H01L2224/05008 , H01L2224/05124 , H01L2224/05548 , H01L2224/05569 , H01L2224/05647 , H01L2224/13 , H01L2924/00014
摘要： A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having “n” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.
摘要翻译： CMOS图像传感器阵列及其制造方法。 CMOS成像器传感器阵列包括衬底; 形成在衬底上方的光接收像素结构的阵列，阵列中形成有“m”级的导电结构，每个级形成在相应的层间介电材料层中; 与具有“n”级的导电结构的光接收像素结构的阵列相邻形成的密集的逻辑布线区域，每个层级形成在相应的层间电介质材料层中，其中n> m。具有形成在层间电介质材料层上方的微透镜和滤色器的微透镜阵列，与形成在衬底表面处的各个光接收结构对准的微透镜和相应的滤色器。微透镜阵列下面的层间介电材料层的顶表面从密集逻辑布线区域的层间介电材料层的顶表面凹陷。

68. 发明授权

US07745863B2 Flip FERAM cell and method to form same 失效
标题翻译：翻转FERAM细胞和方法形成相同
公开(公告)号：US07745863B2
公开(公告)日：2010-06-29
申请号：US12146576
申请日：2008-06-26
申请人： James W. Adkisson , Charles Thomas Black , Alfred Grill , Randy William Mann , Deborah Ann Neumayer , Wilbur David Pricer , Katherine Lynn Saenger , Thomas McCarroll Shaw
发明人： James W. Adkisson , Charles Thomas Black , Alfred Grill , Randy William Mann , Deborah Ann Neumayer , Wilbur David Pricer , Katherine Lynn Saenger , Thomas McCarroll Shaw
IPC分类号： H01L29/82
CPC分类号： H01L28/55 , H01L27/0629 , H01L27/11502 , H01L27/11507 , Y10S438/977
摘要： A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.
摘要翻译：提供了一种形成集成的铁电/ CMOS结构的方法，其有效地分离不兼容的高温沉积和退火工艺。本发明的方法包括分别形成CMOS结构和铁电输送晶片。然后使这些分离的结构与每个结构接触，并且通过使用低温退火步骤将输送晶片的铁电体膜结合到CMOS结构的上导电电极层。然后去除输送晶片的一部分，提供集成的FE / CMOS结构，其中铁电电容器形成在CMOS结构的顶部。电容器通过CMOS结构的所有布线级与CMOS结构的晶体管接触。

69. 发明申请

US20100136733A1 SILICIDE STRAPPING IN IMAGER TRANSFER GATE DEVICE 有权
标题翻译：图像转印门装置中的硅胶缠绕
公开(公告)号：US20100136733A1
公开(公告)日：2010-06-03
申请号：US12699419
申请日：2010-02-03
申请人： James W. Adkisson , John J. Ellis-Monaghan , R. Michael Guidash , Mark D. Jaffe , Edward T. Nelson , Richard J. Rassel , Charles V. Stancampiano
发明人： James W. Adkisson , John J. Ellis-Monaghan , R. Michael Guidash , Mark D. Jaffe , Edward T. Nelson , Richard J. Rassel , Charles V. Stancampiano
IPC分类号： H01L31/18
CPC分类号： H01L27/14609 , H01L27/14643 , H01L27/14689
摘要： A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.
摘要翻译：具有双功能转移栅极器件和制造方法的CMOS有源像素传感器（APS）单元结构。传输栅极器件包括形成在衬底上的电介质层和形成在包括第一导电类型掺杂区和邻接第二导电类型掺杂区的电介质层上的双功函数栅导体层。传输门装置限定了由光敏装置累积的电荷被传送到扩散区的沟道区。在双功函数栅极导体层顶部形成硅化物结构，用于电耦合第一和第二导电类型掺杂区域。在一个实施例中，硅化物接触面积尺寸小于所述双功函数栅极导体层的面积尺寸。硅化物带的存在防止了双极性行为允许栅极的一侧或另一侧浮动到不确定的电压。

70. 发明申请

US20100096536A1 ON DEMAND CIRCUIT FUNCTION EXECUTION EMPLOYING OPTICAL SENSING 有权
标题翻译：使用光电传感器的需求电路功能执行
公开(公告)号：US20100096536A1
公开(公告)日：2010-04-22
申请号：US12646292
申请日：2009-12-23
申请人： Wagdi W. Abadeer , James W. Adkisson , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, JR. , Michael J. Hauser , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , James W. Adkisson , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, JR. , Michael J. Hauser , Jed H. Rankin , William R. Tonti
IPC分类号： G01J1/44
CPC分类号： H01L23/5256 , H01L23/525 , H01L27/14609 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad one the packaged chip is placed in system. No additional pins on the package are necessary.
摘要翻译：公开了通过光谱选择的外部光激活通过芯片嵌入式光电二极管的激活以及相应的结构和电路来执行诸如定影操作之类的电功能的方法。本发明基于将具有特定强度/波长特性的入射光结合到集成电路的附加电路元件，执行维修的实现，即用冗余电路替换故障电路元件以获得和/或可靠性。此外，为了将ESD保护装置与输入板断开，将封装的芯片放置在系统中。不需要额外的引脚。

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