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61. 发明授权

US08586466B2 Electrical fuse with a current shunt 有权
标题翻译：电保险丝与电流分路
公开(公告)号：US08586466B2
公开(公告)日：2013-11-19
申请号：US12967308
申请日：2010-12-14
申请人： Tom C. Lee , Thomas L. McDevitt , William J. Murphy
发明人： Tom C. Lee , Thomas L. McDevitt , William J. Murphy
IPC分类号： H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrical fuses and methods for forming an electrical fuse. The electrical fuse includes a current shunt formed by patterning a first layer comprised of a first conductive material and disposed on a top surface of a dielectric layer. A layer stack is formed on the current shunt and the top surface of the dielectric layer surrounding the current shunt. The layer stack includes a second layer comprised of a second conductive material and a third layer comprised of a third conductive material. The layer stack may be patterned to define a fuse link as a first portion of the layer stack directly contacting the top surface of the dielectric layer and a terminal as a second portion separated from the top surface of the dielectric layer by the current shunt.
摘要翻译：电熔丝和形成电熔丝的方法。电熔丝包括通过图案化由第一导电材料构成的第一层并且设置在电介质层的顶表面上而形成的电流分流器。在电流分路上形成层叠层，并且在电流分路周围形成介电层的顶表面。层叠包括由第二导电材料构成的第二层和由第三导电材料构成的第三层。层叠体可以被图案化以限定作为层叠体的第一部分的熔丝链，其直接接触电介质层的顶表面，并且通过电流分路与端子作为与电介质层的顶表面分离的第二部分。

62. 发明申请

US20120287707A1 OPTOELECTRONIC MEMORY DEVICES 审中-公开
标题翻译：光电存储器件
公开(公告)号：US20120287707A1
公开(公告)日：2012-11-15
申请号：US13558541
申请日：2012-07-26
申请人： Fen Chen , Richard Steven Kontra , Tom C. Lee , Theodore M. Levin , Christopher David Muzzy , Timothy Dooling Sullivan
发明人： Fen Chen , Richard Steven Kontra , Tom C. Lee , Theodore M. Levin , Christopher David Muzzy , Timothy Dooling Sullivan
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： G11C13/0009 , G11C13/0004 , G11C13/004 , G11C13/04 , G11C13/047 , G11C2013/0054 , H01L45/1213 , H01L45/145
摘要： A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value.
摘要翻译：一个结构。该结构包括衬底，衬底上的电阻/反射区域以及被配置为确定电阻/反射区域中的反射率和/或电阻变化的光源/光检测和/或感测放大器电路。电阻/反射区域包括具有材料的反射率和/或电阻的特性的材料由于材料的相变而改变。电阻/反射区域被配置为通过材料的相变来响应通过电阻/反射区域的电流和/或投射在电阻/反射区域上的激光束，这导致反射和/ 电阻/反射区域从第一反射率和/或电阻值到不同于第一反射率和/或电阻值的第二反射率和/或电阻值。

63. 发明申请

US20120128033A1 THERMAL SENSOR FOR SEMICONDUCTOR CIRCUITS 失效
标题翻译：用于半导体电路的热传感器
公开(公告)号：US20120128033A1
公开(公告)日：2012-05-24
申请号：US12950508
申请日：2010-11-19
申请人： Wagdi W. Abadeer , Cathryn J. Christiansen , John A. Fifield , Dimitris P. Ioannou , Tom C. Lee , Lilian Kamal
发明人： Wagdi W. Abadeer , Cathryn J. Christiansen , John A. Fifield , Dimitris P. Ioannou , Tom C. Lee , Lilian Kamal
IPC分类号： G01K7/16
CPC分类号： G01K7/16
摘要： A system and a method for measuring temperature within an operating circuit use a Wheatstone bridge within a temperature sensing circuit. One of the resistors in the Wheatstone bridge is a thermally sensitive resistive material layer within the operating circuit. The other three resistors are thermally isolated from the operating circuit. Particular configurations of NFET and PFET devices are used to provide enhanced measurement sensitivity within the temperature sensing circuit that includes the Wheatstone bridge.
摘要翻译：用于测量操作电路内的温度的系统和方法使用温度感测电路内的惠斯通电桥。惠斯通电桥中的一个电阻器是操作电路内的热敏电阻材料层。其他三个电阻器与工作电路热绝缘。 NFET和PFET器件的特殊配置用于在包括惠斯通电桥的温度检测电路中提供增强的测量灵敏度。

64. 发明授权

US08003536B2 Electromigration resistant aluminum-based metal interconnect structure 有权
公开(公告)号：US08003536B2
公开(公告)日：2011-08-23
申请号：US12552641
申请日：2009-09-02
申请人： Jonathan D. Chapple-Sokol , Daniel A. Delibac , Zhong-Xiang He , Tom C. Lee , William J. Murphy , Timothy D. Sullivan , David C. Thomas , Daniel S. Vanslette
发明人： Jonathan D. Chapple-Sokol , Daniel A. Delibac , Zhong-Xiang He , Tom C. Lee , William J. Murphy , Timothy D. Sullivan , David C. Thomas , Daniel S. Vanslette
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/32051 , H01L21/76846 , H01L21/7685 , H01L21/76858 , H01L2221/1078
摘要： A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.

65. 发明申请

US20100237503A1 ELECTROMIGRATION RESISTANT ALUMINUM-BASED METAL INTERCONNECT STRUCTURE 有权
标题翻译：基于电阻的基于铝的金属互连结构
公开(公告)号：US20100237503A1
公开(公告)日：2010-09-23
申请号：US12552641
申请日：2009-09-02
申请人： Jonathan D. Chapple-Sokol , Daniel A. Delibac , Zhong-Xiang He , Tom C. Lee , William J. Murphy , Timothy D. Sullivan , David C. Thomas , Daniel S. Vanslette
发明人： Jonathan D. Chapple-Sokol , Daniel A. Delibac , Zhong-Xiang He , Tom C. Lee , William J. Murphy , Timothy D. Sullivan , David C. Thomas , Daniel S. Vanslette
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76834 , H01L21/32051 , H01L21/76846 , H01L21/7685 , H01L21/76858 , H01L2221/1078
摘要： A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.
摘要翻译：在下面的金属互连结构上形成由元素金属衬垫，金属氮化物衬垫，Ti衬垫，铝部分和金属氮化物盖的从底部到顶部的垂直金属堆叠。垂直金属叠层在升高的温度下退火，以通过Ti衬垫与铝部分的材料反应而引起TiAl 3衬层的形成。 TiAl 3衬垫的材料对电迁移是耐受的，从而对包括元素金属衬垫，金属氮化物衬垫，TiAl 3衬里，铝部分和金属氮化物盖的垂直金属堆叠提供增强的电迁移阻力。在金属氮化物盖在加工过程中遭受侵蚀的区域中，增强的耐电迁移性的作用可能更为突出。

66. 发明授权

US07512506B2 IC chip stress testing 失效
标题翻译： IC芯片压力测试
公开(公告)号：US07512506B2
公开(公告)日：2009-03-31
申请号：US11755827
申请日：2007-05-31
申请人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
发明人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
IPC分类号： G06F19/00 , G01R31/26
CPC分类号： G01R31/2858 , G01R31/2875 , G01R31/2879
摘要： Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current Is to the line; and stress testing the line while applying the constant current Is such that the constant current Is is not altered by a resistance change due to an onset of electromigration.
摘要翻译：公开了用于对集成电路（IC）芯片中的线进行压力测试的方法，系统和程序产品。该方法的一个实施例包括：对线路施加恒定电流Is; 并且在施加恒定电流Is的同时对线进行应力测试，使得恒定电流Is不会由于电迁移开始时的电阻变化而改变。

67. 发明授权

US08592941B2 Fuse structure having crack stop void, method for forming and programming same, and design structure 有权
标题翻译：具有裂纹阻挡的保险丝结构，其形成和编程方法以及设计结构
公开(公告)号：US08592941B2
公开(公告)日：2013-11-26
申请号：US12838850
申请日：2010-07-19
申请人： Jeffrey P. Gambino , Tom C. Lee , Kevin G. Petrunich , David C. Thomas
发明人： Jeffrey P. Gambino , Tom C. Lee , Kevin G. Petrunich , David C. Thomas
IPC分类号： H01L21/82 , H01L21/326 , H01L21/44 , H01L23/52
CPC分类号： H01L27/11206 , H01L23/5258 , H01L27/112 , H01L2924/0002 , H01L2924/00
摘要： The disclosure relates generally to fuse structures, methods of forming and programming the same, and more particularly to fuse structures having crack stop voids. The fuse structure includes a semiconductor substrate having a dielectric layer thereon and a crack stop void. The dielectric layer includes at least one fuse therein and the crack stop void is adjacent to two opposite sides of the fuse, and extends lower than a bottom surface and above a top surface of the fuse. The disclosure also relates to a design structure of the aforementioned.
摘要翻译：本公开一般涉及熔丝结构，其形成和编程的方法，更具体地涉及具有裂纹停止空隙的熔断结构。熔丝结构包括其上具有介电层的半导体衬底和裂纹阻挡空隙。电介质层包括至少一个熔断器，裂纹阻挡空隙与保险丝的两个相对的两侧相邻，并且比底表面和保险丝顶表面之上延伸。本公开还涉及上述的设计结构。

68. 发明授权

US08563336B2 Method for forming thin film resistor and terminal bond pad simultaneously 有权
标题翻译：同时形成薄膜电阻和端子焊盘的方法
公开(公告)号：US08563336B2
公开(公告)日：2013-10-22
申请号：US12342430
申请日：2008-12-23
申请人： Fen Chen , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee , John C. Malinowski , Anthony K. Stamper
发明人： Fen Chen , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee , John C. Malinowski , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： H01L28/20 , H01C7/006 , H01C17/075 , H01L21/7685 , H01L23/5228 , H01L23/53295 , H01L24/11 , H01L28/24 , H01L2224/0231 , H01L2224/02313 , H01L2224/0401 , H01L2224/04042 , H01L2224/05181 , H01L2224/05546 , H01L2224/05624 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01016 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01073 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/19043 , H01L2924/00014 , H01L2924/013
摘要： Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.
摘要翻译：公开了同时形成薄膜电阻器和端子接合焊盘的方法。一种方法包括在端子线上同时形成端子接合焊盘和在另外两条导线上形成薄膜电阻器。

69. 发明授权

US08236655B2 Fuse link structures using film stress for programming and methods of manufacture 有权
标题翻译：使用膜应力的熔断器连接结构进行编程和制造方法
公开(公告)号：US08236655B2
公开(公告)日：2012-08-07
申请号：US12939538
申请日：2010-11-04
申请人： Karl W. Barth , Jeffrey P. Gambino , Tom C. Lee , Kevin S. Petrarca
发明人： Karl W. Barth , Jeffrey P. Gambino , Tom C. Lee , Kevin S. Petrarca
IPC分类号： H01L21/336
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, forming an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.
摘要翻译：形成可编程熔丝结构的方法包括在衬底中形成至少一个浅沟槽隔离（STI），在至少一个STI上形成e-熔丝，并在该电熔丝上沉积层间电介质（ILD）层。另外，该方法包括移除电子熔丝下的至少一个STI的至少一部分以在e熔丝的一部分下方提供空气间隙，并将e-fuse上的ILD层的至少一部分移除到在电子熔断器的部分上方提供气隙。

70. 发明授权

US08089105B2 Fuse link structures using film stress for programming and methods of manufacture 有权
标题翻译：使用膜应力的熔断器连接结构进行编程和制造方法
公开(公告)号：US08089105B2
公开(公告)日：2012-01-03
申请号：US12939520
申请日：2010-11-04
申请人： Karl W. Barth , Jeffrey P. Gambino , Tom C. Lee , Kevin S. Petrarca
发明人： Karl W. Barth , Jeffrey P. Gambino , Tom C. Lee , Kevin S. Petrarca
IPC分类号： H01L27/10
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, fanning an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.
摘要翻译：形成可编程熔丝结构的方法包括：在衬底中形成至少一个浅沟槽隔离（STI），在所述至少一个STI上扇形e熔丝，并在所述e熔丝上沉积层间电介质（ILD）层。另外，该方法包括移除电子熔丝下的至少一个STI的至少一部分以在e熔丝的一部分下方提供空气间隙，并将e-fuse上的ILD层的至少一部分移除到在电子熔断器的部分上方提供气隙。

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