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    • 3. 发明授权
    • DRAM-based separate I/O memory solution for communication applications
    • 基于DRAM的单独I / O存储器解决方案,用于通信应用
    • US06854041B2
    • 2005-02-08
    • US10065839
    • 2002-11-25
    • James J. CovinoKevin G. PetrunichHarold Pilo
    • James J. CovinoKevin G. PetrunichHarold Pilo
    • G11C7/10G11C7/22G11C11/406G11C11/409G06F13/14
    • G11C11/40618G11C7/1042G11C7/22G11C11/406G11C11/409
    • A structure and method for performing back-to-back read and write memory operations to a same DRAM bank comprising articulating between reading data on a first bank during successive first bank read cycles and writing data to a second bank during successive second bank write cycles, cycling between reading data on the second bank during successive second bank read cycles and writing data to the first bank during successive first bank write cycles, and performing a refresh cycle on the first and second bank, wherein the first bank write cycles lag the first bank read cycles, and wherein the second bank write cycles lag the second bank read cycles. Moreover, the read and write memory operations constantly swap between the read and write cycles and between the first and second bank.
    • 一种用于对同一DRAM组执行背靠背读和写存储器操作的结构和方法,包括在连续的第一存储体读周期期间在第一存储体上读取数据和在连续的第二存储体写周期期间将数据写入第二存储体的关系, 在连续的第二组读取周期期间在第二组上的读取数据之间循环,并且在连续的第一组写周期期间将数据写入第一组,并且在第一和第二组上执行刷新周期,其中第一组写入周期落后于第一组 读周期,并且其中第二存储体写周期滞后于第二存储体读周期。 此外,读和写存储器操作在读和写周期之间以及第一和第二存储体之间不断地交换。