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1. 发明申请

US20120128033A1 THERMAL SENSOR FOR SEMICONDUCTOR CIRCUITS 失效
标题翻译：用于半导体电路的热传感器
公开(公告)号：US20120128033A1
公开(公告)日：2012-05-24
申请号：US12950508
申请日：2010-11-19
申请人： Wagdi W. Abadeer , Cathryn J. Christiansen , John A. Fifield , Dimitris P. Ioannou , Tom C. Lee , Lilian Kamal
发明人： Wagdi W. Abadeer , Cathryn J. Christiansen , John A. Fifield , Dimitris P. Ioannou , Tom C. Lee , Lilian Kamal
IPC分类号： G01K7/16
CPC分类号： G01K7/16
摘要： A system and a method for measuring temperature within an operating circuit use a Wheatstone bridge within a temperature sensing circuit. One of the resistors in the Wheatstone bridge is a thermally sensitive resistive material layer within the operating circuit. The other three resistors are thermally isolated from the operating circuit. Particular configurations of NFET and PFET devices are used to provide enhanced measurement sensitivity within the temperature sensing circuit that includes the Wheatstone bridge.
摘要翻译：用于测量操作电路内的温度的系统和方法使用温度感测电路内的惠斯通电桥。惠斯通电桥中的一个电阻器是操作电路内的热敏电阻材料层。其他三个电阻器与工作电路热绝缘。 NFET和PFET器件的特殊配置用于在包括惠斯通电桥的温度检测电路中提供增强的测量灵敏度。

2. 发明授权

US08562210B2 Thermal sensor for semiconductor circuits 失效
标题翻译：半导体电路用热传感器
公开(公告)号：US08562210B2
公开(公告)日：2013-10-22
申请号：US12950508
申请日：2010-11-19
申请人： Cathryn J. Christiansen , John A. Fifield , Dimitris P. Ioannou , Tom C. Lee , Lilian Kamal
发明人： Wagdi W. Abadeer , Cathryn J. Christiansen , John A. Fifield , Dimitris P. Ioannou , Tom C. Lee
IPC分类号： G01K7/01 , G01K7/14 , G01K7/16 , G01K7/21
CPC分类号： G01K7/16
摘要： A system and a method for measuring temperature within an operating circuit use a Wheatstone bridge within a temperature sensing circuit. One of the resistors in the Wheatstone bridge is a thermally sensitive resistive material layer within the operating circuit. The other three resistors are thermally isolated from the operating circuit. Particular configurations of NFET and PFET devices are used to provide enhanced measurement sensitivity within the temperature sensing circuit that includes the Wheatstone bridge.
摘要翻译：用于测量操作电路内的温度的系统和方法使用温度感测电路内的惠斯通电桥。惠斯通电桥中的一个电阻器是操作电路内的热敏电阻材料层。其他三个电阻器与工作电路热绝缘。 NFET和PFET器件的特殊配置用于在包括惠斯通电桥的温度检测电路中提供增强的测量灵敏度。

3. 发明授权

US07873921B2 Structure for a voltage detection circuit in an integrated circuit and method of generating a trigger flag signal 有权
标题翻译：集成电路中的电压检测电路的结构和产生触发标志信号的方法
公开(公告)号：US07873921B2
公开(公告)日：2011-01-18
申请号：US11948308
申请日：2007-11-30
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
IPC分类号： G06F17/50 , H03L7/00
CPC分类号： G06F17/5063 , G06F2217/78
摘要： A design structure for an integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.
摘要翻译：一种用于集成电路的设计结构，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

4. 发明授权

US07825469B2 Threshold voltage compensation for pixel design of CMOS image sensors 有权
标题翻译： CMOS图像传感器的像素设计阈值电压补偿
公开(公告)号：US07825469B2
公开(公告)日：2010-11-02
申请号：US11850488
申请日：2007-09-05
申请人： Wagdi W. Abadeer , John A. Fifield
发明人： Wagdi W. Abadeer , John A. Fifield
IPC分类号： H01L29/72
CPC分类号： H04N5/374 , H04N5/365 , H04N5/3651 , H04N5/378
摘要： The present disclosure is directed to a CMOS active pixel sensor that compensates for variations in a threshold voltage of a source follower contained therein. A structure in accordance with an embodiment includes: a replica source follower transistor; a system for creating a current in said replica source follower transistor such that a gate-source voltage of said replica source follower is substantially equal to a threshold voltage of said replica source follower; and a current mirror for biasing the isolation source follower transistor at a same current density as the replica source follower transistor.
摘要翻译：本公开涉及一种CMOS有源像素传感器，其补偿其中包含的源极跟随器的阈值电压的变化。根据实施例的结构包括：复制源极跟随器晶体管; 用于在所述复制源跟随器晶体管中产生电流的系统，使得所述复制源极跟随器的栅极 - 源极电压基本上等于所述复制源极跟随器的阈值电压; 以及电流镜，用于以与复制源极跟随器晶体管相同的电流密度偏置隔离源跟随器晶体管。

5. 发明申请

US20090243733A1 DESIGN STRUCTURE FOR TRANSFORMING AN INPUT VOLTAGE TO OBTAIN LINEARITY BETWEEN INPUT AND OUTPUT FUNCTIONS AND SYSTEM AND METHOD THEREOF 有权
标题翻译：用于变换输入电压以获得输入和输出功能与系统之间的线性的设计结构及其方法
公开(公告)号：US20090243733A1
公开(公告)日：2009-10-01
申请号：US12057686
申请日：2008-03-28
申请人： Wagdi W. Abadeer , John A. Fifield , Stephen D. Wyatt
发明人： Wagdi W. Abadeer , John A. Fifield , Stephen D. Wyatt
IPC分类号： H03L7/00
CPC分类号： H03L7/099
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a first structure for determining a non-linear characteristic of the input voltage to the output frequency response, the first design structure providing a tunneling-based current relationship with the input voltage. Also disclosed is a system and a method of implementing such structure.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括用于确定输入电压对输出频率响应的非线性特性的第一结构，第一设计结构提供与输入电压的基于隧道的电流关系。还公开了一种实现这种结构的系统和方法。

6. 发明授权

US07167053B2 Integrated circuit amplifier device and method using FET tunneling gate current 失效
标题翻译：集成电路放大器器件及使用FET隧道栅极电流的方法
公开(公告)号：US07167053B2
公开(公告)日：2007-01-23
申请号：US10904238
申请日：2004-10-29
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Kiran V. Chatty , John A. Fifield
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Kiran V. Chatty , John A. Fifield
IPC分类号： H03F3/16 , H03F3/45 , H03G3/12
CPC分类号： H03F3/16 , H03F3/45179 , H03F3/505 , H03F2203/45468
摘要： An integrated circuit amplifier includes, in an exemplary embodiment, a first field effect transistor (FET) device configured as a common source amplifier with source degeneration and a second FET device configured as a tunneling gate FET, the tunneling gate FET coupled to the source follower. The tunneling gate FET is further configured so as to set a transconductance of the amplifier and the common source amplifier with source degeneration is configured so as to set an output conductance of the amplifier.
摘要翻译：在示例性实施例中，集成电路放大器包括被配置为具有源极退化的公共源极放大器的第一场效应晶体管（FET）器件和被配置为隧道栅极FET的第二FET器件，所述隧道栅极FET耦合到源极跟随器。隧道栅极FET进一步配置为设置放大器的跨导，并且配置源极退化的公共源极放大器，以便设置放大器的输出电导。

7. 发明授权

US07061308B2 Voltage divider for integrated circuits 失效
标题翻译：用于集成电路的分压器
公开(公告)号：US07061308B2
公开(公告)日：2006-06-13
申请号：US10605466
申请日：2003-10-01
申请人： Wagdi W. Abadeer , John A. Fifield , William R. Tonti
发明人： Wagdi W. Abadeer , John A. Fifield , William R. Tonti
IPC分类号： G05F3/02
CPC分类号： G11C5/147 , H01L27/0802 , H01L27/088 , H02M3/00
摘要： A voltage divider for integrated circuits that does not include the use of resistors. In one embodiment, voltage node VDD is connected with two n-type transistors, NFET1 and NFET2, which are connected in series. NFET 1 includes a source (12), a drain (14), a gate electrode (16) having a gate area A1 (not shown), and a p-substrate (18). NFET2 includes a source (20), a drain (22), a gate electrode (24) having a gate area A2 (not shown), and a p-substrate (26). Source (12) and drain (14) of NFET1 are coupled with gate electrode (24) of NFET2. The voltage difference between NFET1 and NFET2 has a linear function with VDD. As a result, voltage VDD may be divided between NFET1 and NFET2 by properly choosing the ratio between each of the respective transistor gate electrode areas, (A1) and (A2).
摘要翻译：用于集成电路的分压器，不包括使用电阻器。在一个实施例中，电压节点VDD与串联连接的两个n型晶体管NFET 1和NFET 2连接。 NFET 1包括源极（12），漏极（14），具有栅极区域A 1（未示出）的栅电极（16）和p-衬底（18）。 NFET2包括源极（20），漏极（22），具有栅极区域A 2（未示出）的栅电极（24）和p基板（26）。 NFET 1的源极（12）和漏极（14）与NFET2的栅电极（24）耦合。 NFET 1和NFET 2之间的电压差与VDD具有线性关系。结果，通过适当地选择各个晶体管栅电极区域（A 1）和（A 2）之间的比率，可以在NFET 1和NFET 2之间划分电压VDD。

8. 发明授权

US07847605B2 Voltage detection circuit in an integrated circuit and method of generating a trigger flag signal 有权
标题翻译：集成电路中的电压检测电路和产生触发标志信号的方法
公开(公告)号：US07847605B2
公开(公告)日：2010-12-07
申请号：US12242114
申请日：2008-09-30
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
IPC分类号： H03L7/00
CPC分类号： H03K5/153
摘要： An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.
摘要翻译：一种集成电路，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

9. 发明申请

US20090144689A1 Structure for a Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal 有权
标题翻译：集成电路中的电压检测电路的结构和产生触发标志信号的方法
公开(公告)号：US20090144689A1
公开(公告)日：2009-06-04
申请号：US11948308
申请日：2007-11-30
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F2217/78
摘要： A design structure for an integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.
摘要翻译：一种用于集成电路的设计结构，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

10. 发明申请

US20090057804A1 THRESHOLD VOLTAGE COMPENSATION FOR PIXEL DESIGN OF CMOS IMAGE SENSORS 有权
标题翻译： CMOS图像传感器像素设计的阈值电压补偿
公开(公告)号：US20090057804A1
公开(公告)日：2009-03-05
申请号：US11850488
申请日：2007-09-05
申请人： Wagdi W. Abadeer , John A. Fifield
发明人： Wagdi W. Abadeer , John A. Fifield
IPC分类号： H01L31/00 , G06F17/50
CPC分类号： H04N5/374 , H04N5/365 , H04N5/3651 , H04N5/378
摘要： The present disclosure is directed to a CMOS active pixel sensor that compensates for variations in a threshold voltage of a source follower contained therein. A structure in accordance with an embodiment includes: a replica source follower transistor; a system for creating a current in said replica source follower transistor such that a gate-source voltage of said replica source follower is substantially equal to a threshold voltage of said replica source follower; and a current mirror for biasing the isolation source follower transistor at a same current density as the replica source follower transistor.
摘要翻译：本公开涉及一种CMOS有源像素传感器，其补偿其中包含的源极跟随器的阈值电压的变化。根据实施例的结构包括：复制源极跟随器晶体管; 用于在所述复制源跟随器晶体管中产生电流的系统，使得所述复制源极跟随器的栅极 - 源极电压基本上等于所述复制源极跟随器的阈值电压; 以及电流镜，用于以与复制源极跟随器晶体管相同的电流密度偏置隔离源跟随器晶体管。

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