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61. 发明授权

US08604853B1 State retention supply voltage distribution using clock network shielding 有权
标题翻译：状态保持电源电压分配采用时钟网络屏蔽
公开(公告)号：US08604853B1
公开(公告)日：2013-12-10
申请号：US13480971
申请日：2012-05-25
申请人： Anis M. Jarrar , Hector Sanchez
发明人： Anis M. Jarrar , Hector Sanchez
IPC分类号： H03K3/289
CPC分类号： H01L23/5225 , H01L2924/0002 , H03K3/013 , H03K3/0375 , H01L2924/00
摘要： An integrated circuit including a state retention node, a conductive clock network shielding and multiple state retention devices for maintaining a state of the integrated circuit during the low power state. The state retention node receives a state retention supply voltage which remains at an operative voltage level during a low power state. The conductive clock network shielding is distributed with clock signal conductors and is coupled to the state retention node. Each state retention device has a supply voltage input coupled to the clock network shielding so that it remains powered during the low power state. The state retention node may be implemented as a minimal set of conductive traces. A state retention buffer may be provided for buffering a power gating signal indicative of the low power state, in which the buffer has a supply voltage input coupled to the clock network shielding.
摘要翻译：一种集成电路，包括状态保持节点，导电时钟网络屏蔽和用于在低功率状态期间保持集成电路的状态的多个状态保持装置。状态保持节点接收在低功率状态期间保持在工作电压电平的状态保持电源电压。导电时钟网络屏蔽与时钟信号导体一起分布并耦合到状态保持节点。每个状态保持装置具有耦合到时钟网络屏蔽的电源电压输入，使得它在低功率状态期间保持供电。状态保持节点可以被实现为导电迹线的最小集合。可以提供状态保持缓冲器用于缓冲表示低功率状态的电源门控信号，其中缓冲器具有耦合到时钟网络屏蔽的电源电压输入。

62. 发明申请

US20130314138A1 STATE RETENTION SUPPLY VOLTAGE DISTRIBUTION USING CLOCK NETWORK SHIELDING 有权
标题翻译：使用时钟网络屏蔽的状态保持电源分配
公开(公告)号：US20130314138A1
公开(公告)日：2013-11-28
申请号：US13480971
申请日：2012-05-25
申请人： Anis M. Jarrar , Hector Sanchez
发明人： Anis M. Jarrar , Hector Sanchez
IPC分类号： H03K3/289 , G05F3/02 , H03K17/56
CPC分类号： H01L23/5225 , H01L2924/0002 , H03K3/013 , H03K3/0375 , H01L2924/00
摘要： An integrated circuit including a state retention node, a conductive clock network shielding and multiple state retention devices for maintaining a state of the integrated circuit during the low power state. The state retention node receives a state retention supply voltage which remains at an operative voltage level during a low power state. The conductive clock network shielding is distributed with clock signal conductors and is coupled to the state retention node. Each state retention device has a supply voltage input coupled to the clock network shielding so that it remains powered during the low power state. The state retention node may be implemented as a minimal set of conductive traces. A state retention buffer may be provided for buffering a power gating signal indicative of the low power state, in which the buffer has a supply voltage input coupled to the clock network shielding.
摘要翻译：一种集成电路，包括状态保持节点，导电时钟网络屏蔽和用于在低功率状态期间保持集成电路的状态的多个状态保持装置。状态保持节点接收在低功率状态期间保持在工作电压电平的状态保持电源电压。导电时钟网络屏蔽与时钟信号导体一起分布并耦合到状态保持节点。每个状态保持装置具有耦合到时钟网络屏蔽的电源电压输入，使得它在低功率状态期间保持供电。状态保持节点可以被实现为导电迹线的最小集合。可以提供状态保持缓冲器用于缓冲表示低功率状态的电源门控信号，其中缓冲器具有耦合到时钟网络屏蔽的电源电压输入。

63. 发明授权

US08324882B2 Phase locked loop device and method thereof 有权
标题翻译：锁相环装置及其方法
公开(公告)号：US08324882B2
公开(公告)日：2012-12-04
申请号：US12480311
申请日：2009-06-08
申请人： Gayathri A. Bhagavatheeswaran , Lipeng Cao , Hector Sanchez
发明人： Gayathri A. Bhagavatheeswaran , Lipeng Cao , Hector Sanchez
IPC分类号： G01R23/175
CPC分类号： G01R25/005
摘要： A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal of the phase locked loop. The phase detector provides a pulse having a width indicative of the phase difference. A phase measurement module determines a digital value based on the pulse width. Accordingly, the digital value provides an indication of the phase difference between the reference clock signal and the output clock signal. A series of the digital values can be recorded to indicate how the phase difference varies over time, thereby providing a useful characterization of device behavior.
摘要翻译：锁相环装置包括相位检测器，该相位检测器测量基准时钟信号和锁相环的输出时钟信号之间的相位差。相位检测器提供具有指示相位差的宽度的脉冲。相位测量模块基于脉冲宽度确定数字值。因此，数字值提供参考时钟信号和输出时钟信号之间的相位差的指示。可以记录一系列数字值以指示相位差随时间变化，从而提供器件行为的有用表征。

64. 发明申请

US20100310030A1 PHASE LOCKED LOOP DEVICE AND METHOD THEREOF 有权
标题翻译：相位锁定环路装置及其方法
公开(公告)号：US20100310030A1
公开(公告)日：2010-12-09
申请号：US12480344
申请日：2009-06-08
申请人： Gayathri A. Bhagavatheeswaran , Joseph P. Gergen , Arvind Raman , Hector Sanchez
发明人： Gayathri A. Bhagavatheeswaran , Joseph P. Gergen , Arvind Raman , Hector Sanchez
IPC分类号： H03D3/24
CPC分类号： H03D13/00 , G11C7/222 , G11C29/1201 , H03L7/0805
摘要： A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, in indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device.
摘要翻译：锁相环装置包括相位检测器，该相位检测器测量参考时钟信号和提供给器件模块的输出时钟信号之间的相位差。相位检测器提供具有指示相位差的宽度的脉冲。如果相位差超过多个阈值中的一个，则可以确定in指示符。基于指示器，控制模块可以采取补救措施，例如向设备模块提供不同的时钟信号或在处理器设备触发中断。

65. 发明申请

US20070259485A1 Electronic device including semiconductor fins and a process for forming the electronic device 有权
标题翻译：包括半导体散热片的电子设备和用于形成电子设备的方法
公开(公告)号：US20070259485A1
公开(公告)日：2007-11-08
申请号：US11416436
申请日：2006-05-02
申请人： Zhonghai Shi , Bich-Yen Nguyen , Hector Sanchez
发明人： Zhonghai Shi , Bich-Yen Nguyen , Hector Sanchez
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L29/66795
摘要： An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.
摘要翻译：电子设备可以包括与另一个间隔开的第一半导体鳍片和第二半导体鳍片。电子设备还可以分别包括位于第一半导体鳍片和第二半导体鳍片之间并且分别仅与第一半导体鳍片和第二半导体鳍片的每一个的长度的一部分接触的桥接器。在另一方面，一种用于形成电子器件的方法可以包括从半导体层形成第一半导体鳍片和第二半导体鳍片，每个第一半导体鳍片和第二半导体鳍片彼此间隔开。该工艺还可以包括形成接触第一半导体鳍片和第二半导体鳍片的桥。该方法还可以包括形成位于第一半导体鳍片和第二半导体鳍片之间的包括栅电极的导电构件。

66. 发明授权

US07279997B2 Voltage controlled oscillator with a multiple gate transistor and method therefor 有权
公开(公告)号：US07279997B2
公开(公告)日：2007-10-09
申请号：US11250994
申请日：2005-10-14
申请人： Sriram S. Kalpat , Leo Mathew , Mohamed S. Moosa , Michael A. Sadd , Hector Sanchez
发明人： Sriram S. Kalpat , Leo Mathew , Mohamed S. Moosa , Michael A. Sadd , Hector Sanchez
IPC分类号： H03L7/099
CPC分类号： H01L27/1211 , H01L29/66795 , H01L29/785 , H03K5/133 , H03K2005/00026 , H03K2005/00058 , H03L7/0995
摘要： A voltage controlled oscillator (VCO) has a plurality of series-connected inverters. Within each inverter a first transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of series-connected inverters, and a second control electrode for receiving a first bias signal. A second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal, and a first control electrode coupled to the first control electrode of the first transistor. The second control electrode of the first transistor of each inverter receives a same or separate analog control signal to adjust the threshold voltage of the first transistors thereof to affect frequency and phase of the VCO's signal.

67. 发明申请

US20050042867A1 Semiconductor device having electrical contact from opposite sides 有权
标题翻译：具有来自相对侧的电接触的半导体器件
公开(公告)号：US20050042867A1
公开(公告)日：2005-02-24
申请号：US10946758
申请日：2004-09-22
申请人： Hector Sanchez , Michael Mendicino , Byoung Min , Kathleen Yu
发明人： Hector Sanchez , Michael Mendicino , Byoung Min , Kathleen Yu
IPC分类号： H01L21/02 , H01L21/768 , H01L21/84 , H01L23/48 , H01L23/522 , H01L27/06 , H01L27/12 , H01L21/20
CPC分类号： H01L27/0688 , H01L21/76838 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.
摘要翻译：半导体（10）具有诸如晶体管的有源器件，其具有通过通孔或导电区域（52）和互连（68）连接的直接下伏的无源器件，例如电容器（75,77,79），99）。通孔或导电区域（52）接触晶体管的扩散或源极区域（22）的底表面并与第一（75）电容器电极接触。横向定位的垂直通孔（32,54,68）和互连件（99）接触电容器电极的第二（79）。金属互连或导电材料（68）可以用作通过在晶体管下面实现功率平面而不是与晶体管相邻来节省电路面积的功率面。

68. 发明申请

US20050035459A1 Semiconductor device having a multiple thickness interconnect 有权
标题翻译：具有多重厚度互连的半导体器件
公开(公告)号：US20050035459A1
公开(公告)日：2005-02-17
申请号：US10946675
申请日：2004-09-22
申请人： Kathleen Yu , Kirk Strozewski , Janos Farkas , Hector Sanchez , Yeong-Jyh Lii
发明人： Kathleen Yu , Kirk Strozewski , Janos Farkas , Hector Sanchez , Yeong-Jyh Lii
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/528 , H01L21/4763 , H01L21/44 , H01L29/40
CPC分类号： H01L23/5283 , H01L21/76807 , H01L21/76816 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.
摘要翻译：导线的厚度变化，有助于克服RC延迟和噪声耦合。通过改变线路厚度，如果需要在导体之间保持规定的最小间距，同时保持预定的期望的RC参数和导线的噪声特性，则避免导体宽度的变化。通过将介电层蚀刻成不同的厚度来实现导体深度变化。电介质层上的不同厚度的导电填充导致厚度变化的导线。在特定金属水平可用的不同的导线厚度可以另外用于除信号或电源导线之外的半导体结构，例如器件的触点，通孔或电极。为了满足期望的设计标准，确定互连厚度如何变化所需的厚度分析可以是自动化的并且作为CAD工具提供。

69. 发明授权

US06838332B1 Method for forming a semiconductor device having electrical contact from opposite sides 有权
标题翻译：用于形成具有来自相对侧的电接触的半导体器件的方法
公开(公告)号：US06838332B1
公开(公告)日：2005-01-04
申请号：US10641544
申请日：2003-08-15
申请人： Hector Sanchez , Michael A. Mendicino , Byoung W. Min , Kathleen C. Yu
发明人： Hector Sanchez , Michael A. Mendicino , Byoung W. Min , Kathleen C. Yu
IPC分类号： H01L21/02 , H01L21/768 , H01L21/84 , H01L23/48 , H01L23/522 , H01L27/06 , H01L27/12 , H01L21/8242 , H01L21/20 , H01L21/4763
CPC分类号： H01L27/0688 , H01L21/76838 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.
摘要翻译：半导体（10）具有诸如晶体管的有源器件，其具有通过通孔或导电区域（52）和互连（68）连接的直接下伏的无源器件，例如电容器（75,77,79），99）。通孔或导电区域（52）接触晶体管的扩散或源极区域（22）的底表面并与第一（75）电容器电极接触。横向定位的垂直通孔（32,54,68）和互连件（99）接触电容器电极的第二（79）。金属互连或导电材料（68）可以用作通过在晶体管下面实现功率平面而不是与晶体管相邻来节省电路面积的功率面。

70. 发明授权

US6160305A Beta dependent temperature sensor for an integrated circuit 失效
标题翻译：用于集成电路的Beta相关温度传感器
公开(公告)号：US6160305A
公开(公告)日：2000-12-12
申请号：US777924
申请日：1996-12-23
申请人： Hector Sanchez
发明人： Hector Sanchez
IPC分类号： G01K7/01 , H01L27/06 , H01L31/058 , H01L27/082 , H01L27/102 , H01L29/70
CPC分类号： G01K7/01 , H01L27/0623
摘要： A thermal sensing element (10) incorporates a vertical pnp bipolar transistor (12) whose BETA is dependent on temperature. This known relationship can be used to build a temperature sensor (200, 300), that is inexpensive, reliable, and whose process variance is predictable.
摘要翻译：热敏元件（10）包含其BETA取决于温度的垂直pnp双极晶体管（12）。这种已知的关系可用于构建廉价，可靠的温度传感器（200,300），并且其工艺方差是可预测的。

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