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1. 发明申请

US20070259485A1 Electronic device including semiconductor fins and a process for forming the electronic device 有权
标题翻译：包括半导体散热片的电子设备和用于形成电子设备的方法
公开(公告)号：US20070259485A1
公开(公告)日：2007-11-08
申请号：US11416436
申请日：2006-05-02
申请人： Zhonghai Shi , Bich-Yen Nguyen , Hector Sanchez
发明人： Zhonghai Shi , Bich-Yen Nguyen , Hector Sanchez
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L29/66795
摘要： An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.
摘要翻译：电子设备可以包括与另一个间隔开的第一半导体鳍片和第二半导体鳍片。电子设备还可以分别包括位于第一半导体鳍片和第二半导体鳍片之间并且分别仅与第一半导体鳍片和第二半导体鳍片的每一个的长度的一部分接触的桥接器。在另一方面，一种用于形成电子器件的方法可以包括从半导体层形成第一半导体鳍片和第二半导体鳍片，每个第一半导体鳍片和第二半导体鳍片彼此间隔开。该工艺还可以包括形成接触第一半导体鳍片和第二半导体鳍片的桥。该方法还可以包括形成位于第一半导体鳍片和第二半导体鳍片之间的包括栅电极的导电构件。

2. 发明申请

US20070085624A1 Voltage controlled oscillator having digitally controlled phase adjustment and method therefor 有权
公开(公告)号：US20070085624A1
公开(公告)日：2007-04-19
申请号：US11251467
申请日：2005-10-14
申请人： Hector Sanchez , Zhonghai Shi
发明人： Hector Sanchez , Zhonghai Shi
IPC分类号： H03L7/099
CPC分类号： H03L7/0995 , H01L29/785 , H03K5/133 , H03K2005/00065 , H03L7/089
摘要： A VCO has a plurality of MIGFETs coupled to provide phase adjustment in response to receiving digital phase adjustment control signals. The VCO includes a ring oscillator implemented as a plurality of serially coupled inverters. A phase adjustment circuit is coupled to the output of each inverter. The phase adjustment circuit of each stage comprises a predetermined number of MIGFETs. In one embodiment, half of the MIGFETs are used to speed-up the phase/frequency of the OUTPUT signal a predetermined amount in response to receiving speed-up control signals. The other half of the MIGFETs are used to slow-down the phase/frequency of the OUTPUT signal a predetermined amount in response to the receiving slow-down control signals. The VCO requires relatively less surface area, is simple, and is easy to implement.

3. 发明授权

US07256657B2 Voltage controlled oscillator having digitally controlled phase adjustment and method therefor 有权
标题翻译：具有数字控制相位调节的压控振荡器及其方法
公开(公告)号：US07256657B2
公开(公告)日：2007-08-14
申请号：US11251467
申请日：2005-10-14
申请人： Hector Sanchez , Zhonghai Shi
发明人： Hector Sanchez , Zhonghai Shi
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H01L29/785 , H03K5/133 , H03K2005/00065 , H03L7/089
摘要： A VCO has a plurality of MIGFETs coupled to provide phase adjustment in response to receiving digital phase adjustment control signals. The VCO includes a ring oscillator implemented as a plurality of serially coupled inverters. A phase adjustment circuit is coupled to the output of each inverter. The phase adjustment circuit of each stage comprises a predetermined number of MIGFETs. In one embodiment, half of the MIGFETs are used to speed-up the phase/frequency of the OUTPUT signal a predetermined amount in response to receiving speed-up control signals. The other half of the MIGFETs are used to slow-down the phase/frequency of the OUTPUT signal a predetermined amount in response to the receiving slow-down control signals. The VCO requires relatively less surface area, is simple, and is easy to implement.
摘要翻译： VCO具有耦合以响应于接收数字相位调整控制信号而提供相位调整的多个MIGFET。 VCO包括实现为多个串联耦合的反相器的环形振荡器。相位调整电路与各逆变器的输出端相连。每级的相位调整电路包括预定数量的MIGFET。在一个实施例中，MIGFET的一半用于响应于接收加速控制信号将OUTPUT信号的相位/频率加速预定量。 MIGFET的另一半用于响应于接收到的减速控制信号将OUTPUT信号的相位/频率降低预定量。 VCO需要相对较小的表面积，简单，易于实现。

4. 发明授权

US08823454B2 Fully complementary self-biased differential receiver with startup circuit 有权
标题翻译：具有启动电路的完全互补的自偏置差分接收器
公开(公告)号：US08823454B2
公开(公告)日：2014-09-02
申请号：US13435981
申请日：2012-03-30
申请人： Hector Sanchez
发明人： Hector Sanchez
IPC分类号： H03F3/45
CPC分类号： H03F3/4521 , H03F3/45381 , H03F3/72 , H03F2203/45466 , H03F2203/45674 , H03F2203/7227
摘要： In accordance with at least one embodiment, an improved voltage headroom self-biased receiver is provided. In accordance with at least one embodiment, tail current sources are biased so as to be cross-coupled with respect to each other. In accordance with at least one embodiment, startup control is provided to counter defect-induced current and to ensure the circuit can function properly even with large amounts of defect current. In accordance with at least one embodiment, a positive type (p type) channel metal oxide semiconductor (PMOS) tail current transistor is modulated by a negative type (n type) channel metal oxide semiconductor (NMOS) differential pair virtual negative supply voltage and a NMOS tail current transistor is modulated by a PMOS differential pair virtual positive supply voltage. The amplifier's output common mode is thus self correcting to p type to n type transistor strength differences.
摘要翻译：根据至少一个实施例，提供了改进的电压余量自偏置接收器。根据至少一个实施例，尾电流源被偏置以相对于彼此交叉耦合。根据至少一个实施例，提供启动控制以对抗缺陷感应电流，并且确保即使在大量缺陷电流下电路也能正常工作。根据至少一个实施例，正型（p型）沟道金属氧化物半导体（PMOS）尾电流晶体管由负型（n型）沟道金属氧化物半导体（NMOS）差分对虚拟负电源电压和 NMOS尾电流晶体管由PMOS差分对虚拟正电源电压调制。放大器的输出共模因此自校正为p型至n型晶体管强度差。

5. 发明授权

US08319548B2 Integrated circuit having low power mode voltage regulator 有权
标题翻译：集成电路具有低功耗模式电压调节器
公开(公告)号：US08319548B2
公开(公告)日：2012-11-27
申请号：US12622277
申请日：2009-11-19
申请人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg , Hector Sanchez , Bradley J. Garni
发明人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg , Hector Sanchez , Bradley J. Garni
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , G11C5/147
摘要： A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.
摘要翻译：电压调节器调节节点处的电压，并且具有耦合到节点的电路以向节点提供电流。耦合在节点和第一电源电压端子之间的调节晶体管具有并联耦合的禁用晶体管，并且通过将第一电源电压端子直接连接到节点来选择性地禁止。反相级具有连接到调节晶体管的输出端。负载晶体管具有耦合到第二电源电压端子的第一电流电极和连接在一起并耦合到反相级的输入端的控制电极和第二电流电极。感测晶体管具有耦合到负载晶体管的第二电流电极的第一电流电极，直接连接到节点的控制电极和耦合到第一电源电压端子的第二电流电极。

6. 发明授权

US08094769B2 Phase-locked loop system with a phase-error spreading circuit 有权
标题翻译：具有相位误差扩展电路的锁相环系统
公开(公告)号：US08094769B2
公开(公告)日：2012-01-10
申请号：US12180166
申请日：2008-07-25
申请人： Gayathri A. Bhagavatheeswaran , Lipeng Cao , Hector Sanchez
发明人： Gayathri A. Bhagavatheeswaran , Lipeng Cao , Hector Sanchez
IPC分类号： H03D3/24
CPC分类号： H03L7/099 , H03L7/0891 , H03L2207/06
摘要： A phase-locked loop (PLL) system including a phase-frequency detector for generating an up signal or a down signal based on a phase difference between a reference clock and a feedback clock is provided. The PLL system further includes a phase-error spreading circuit for generating phase-spread pulses based on a relationship between a first time attribute of the up signal or the down signal and a second time attribute of the phase-spread pulses. The PLL system further includes a voltage-controlled oscillator (VCO) for generating a VCO clock based on the phase-spread pulses. The PLL system may also include a charge pump that generates a pumping signal based on the phase-spread pulses.
摘要翻译：提供一种锁相环（PLL）系统，其包括用于基于参考时钟和反馈时钟之间的相位差产生上行信号或下降信号的相位频率检测器。 PLL系统还包括一个相位误差扩展电路，用于根据上升信号或下降信号的第一时间属性与相位扩展脉冲的第二时间属性之间的关系产生相位扩展脉冲。 PLL系统还包括用于基于相位扩展脉冲产生VCO时钟的压控振荡器（VCO）。 PLL系统还可以包括基于相位扩展脉冲产生泵浦信号的电荷泵。

7. 发明授权

US07816948B1 Voltage translator 有权
标题翻译：电压转换器
公开(公告)号：US07816948B1
公开(公告)日：2010-10-19
申请号：US12481319
申请日：2009-06-09
申请人： Hector Sanchez
发明人： Hector Sanchez
IPC分类号： H03K19/0175
CPC分类号： H03K19/018507 , H03K3/037
摘要： A voltage translator having an input which receives an input signal and an output which provides a level shifted output signal includes a first inverter having an input coupled to receive the input signal, a second inverter having an input coupled to an output of the first inverter, a third inverter having an input coupled to an output of the second inverter, a fourth inverter having an input coupled to receive the input signal and an output coupled to an output of the third inverter, a fifth inverter having an input coupled to an output of the fourth inverter and having an output coupled to the input of the third inverter, and a sixth inverter having an input coupled to the output of the fifth inverter and an output coupled to the output of the voltage translator. The second and fourth inverters are coupled to a calibration voltage supply terminal.
摘要翻译：具有接收输入信号的输入端和提供电平移位输出信号的输出的电压转换器包括具有耦合以接收输入信号的输入的第一反相器，具有耦合到第一反相器的输出的输入的第二反相器，具有耦合到所述第二反相器的输出的输入的第三反相器，具有耦合以接收所述输入信号的输入和耦合到所述第三反相器的输出的输出的第四反相器，具有耦合到所述第三反相器的输出的输入的第五反相器所述第四反相器具有耦合到所述第三反相器的输入的输出，以及第六反相器，具有耦合到所述第五反相器的输出的输入端和耦合到所述电压转换器的输出的输出。第二和第四反相器耦合到校准电压提供端子。

8. 发明授权

US07176574B2 Semiconductor device having a multiple thickness interconnect 有权
标题翻译：具有多重厚度互连的半导体器件
公开(公告)号：US07176574B2
公开(公告)日：2007-02-13
申请号：US10946675
申请日：2004-09-22
申请人： Kathleen C. Yu , Kirk J. Strozewski , Janos Farkas , Hector Sanchez , Yeong-Jyh T. Lii
发明人： Kathleen C. Yu , Kirk J. Strozewski , Janos Farkas , Hector Sanchez , Yeong-Jyh T. Lii
IPC分类号： H01L23/52
CPC分类号： H01L23/5283 , H01L21/76807 , H01L21/76816 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.
摘要翻译：导线的厚度变化，有助于克服RC延迟和噪声耦合。通过改变线路厚度，如果需要在导体之间保持规定的最小间距，同时保持预定的期望的RC参数和导线的噪声特性，则避免导体宽度的变化。通过将介电层蚀刻成不同的厚度来实现导体深度变化。电介质层上的不同厚度的导电填充导致厚度变化的导线。在特定金属水平可用的不同的导线厚度可以另外用于除信号或电源导线之外的半导体结构，例如器件的触点，通孔或电极。为了满足期望的设计标准，确定互连厚度如何变化所需的厚度分析可以是自动化的并且作为CAD工具提供。

9. 发明申请

US20070001716A1 High speed output buffer with AC-coupled level shift and DC level detection and correction 有权
公开(公告)号：US20070001716A1
公开(公告)日：2007-01-04
申请号：US11169862
申请日：2005-06-29
申请人： Hector Sanchez , Xinghai Tang , Carlos Greaves , Jim Nissen
发明人： Hector Sanchez , Xinghai Tang , Carlos Greaves , Jim Nissen
IPC分类号： H03B1/00
CPC分类号： H03K19/00315 , H03K19/018585
摘要： A high speed output buffer including an input circuit providing first and second signals within a first voltage range having a first common mode voltage, an AC interface receiving the first and second signals and providing first and second preliminary drive signals, a detection and correction circuit that corrects a state of the first preliminary drive signal AC coupled to the first signal, first and second drive circuits receiving the preliminary drive signals and providing first and second drive signals, where the first drive circuit operates within a second voltage range having a greater common mode voltage and where the second drive circuit operates within a third voltage range, and an output that switches an output node within a voltage range that is greater than a maximum voltage range. The first, second and third voltage ranges are each within the maximum voltage range suitable for thin-gate devices.

10. 发明申请

US20050280088A1 Backside body contact 审中-公开
标题翻译：背部身体接触
公开(公告)号：US20050280088A1
公开(公告)日：2005-12-22
申请号：US10872025
申请日：2004-06-18
申请人： Byoung Min , Scott Pozder , Hector Sanchez
发明人： Byoung Min , Scott Pozder , Hector Sanchez
IPC分类号： H01L27/01 , H01L27/12 , H01L29/786
CPC分类号： H01L29/78615 , H01L21/743 , H01L21/76898 , H01L27/1203 , H01L29/78648
摘要： A back side body contact for a transistor that extends through an opening in an insulating layer located adjacent to the backside of the body. The backside contact is coupled to an interconnect on the backside. In some examples, the interconnect is coupled to an interconnect located with respect the other side of an active layer which is coupled to a body voltage bias source.
摘要翻译：用于晶体管的背侧体接触，其延伸穿过位于邻近身体背侧的绝缘层中的开口。背面触点耦合到背面的互连。在一些示例中，互连耦合到相对于耦合到体电压偏压源的有源层的另一侧定位的互连。

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