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61. 发明授权

US08102691B2 Magnetic tracks with domain wall storage anchors 有权
标题翻译：具有域墙存储锚的磁迹
公开(公告)号：US08102691B2
公开(公告)日：2012-01-24
申请号：US12144705
申请日：2008-06-24
申请人： Haiwen Xi , Xiaobin Wang , Dimitar V. Dimitrov , Paul E. Anderson , Harry Liu , Song S. Xue , Andreas Roelofs , Markus Siegert
发明人： Haiwen Xi , Xiaobin Wang , Dimitar V. Dimitrov , Paul E. Anderson , Harry Liu , Song S. Xue , Andreas Roelofs , Markus Siegert
IPC分类号： G11C19/00
CPC分类号： G11C19/0808 , G11C11/14 , Y10S977/933
摘要： Magnetic shift registers in which data writing and reading is accomplished by moving the magnetic domain walls by electric current. Various embodiments of domain wall nodes or anchors that stabilize a domain wall are provided. In some embodiments, the wall anchors are elements separate from the magnetic track. In other embodiments, the wall anchors are disturbances in the physical configuration of the magnetic track. In still other embodiments, the wall anchors are disturbances in the material of the magnetic track.
摘要翻译：磁性移位寄存器，其中通过电流移动磁畴壁来实现数据写入和读取。提供了稳定域壁的畴壁节点或锚的各种实施例。在一些实施例中，壁锚是与磁迹分离的元件。在其他实施例中，壁锚是磁轨的物理构型的扰动。在另外的其它实施例中，壁锚是磁迹材料中的干扰。

62. 发明申请

US20110090733A1 MEMORY WITH SEPARATE READ AND WRITE PATHS 有权
标题翻译：具有单独读取和写入数据的存储器
公开(公告)号：US20110090733A1
公开(公告)日：2011-04-21
申请号：US12974679
申请日：2010-12-21
申请人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
发明人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
IPC分类号： G11C11/15
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.
摘要翻译：存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。磁性隧道结数据单元电耦合在读取位线和读取源极线之间。磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。写入电流通过巨磁电阻单元，以在高电阻状态和低电阻状态之间切换巨磁电阻单元。磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

63. 发明授权

US07881098B2 Memory with separate read and write paths 有权
标题翻译：内存具有单独的读写路径
公开(公告)号：US07881098B2
公开(公告)日：2011-02-01
申请号：US12198416
申请日：2008-08-26
申请人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
发明人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
IPC分类号： G11C11/00
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line and a magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line. A write current passing through the giant magnetoresistance cell switches the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell. The magnetic tunnel junction data cell is read by a read current passing though the magnetic tunnel junction data cell.
摘要翻译：存储单元包括电耦合在写位线和写入源线之间的电磁耦合单元和电耦合在读取位线和读取源极线之间的磁性隧道结数据单元的巨磁电阻单元。通过巨磁电阻单元的写入电流将巨磁阻单元切换到高电阻状态和低电阻状态之间。磁隧道结数据单元被配置为通过与巨磁阻单元的静磁耦合在高电阻状态和低电阻状态之间切换。磁隧道结数据单元由通过磁性隧道结数据单元的读取电流读取。

64. 发明授权

US07852663B2 Nonvolatile programmable logic gates and adders 有权
标题翻译：非易失性可编程逻辑门和加法器
公开(公告)号：US07852663B2
公开(公告)日：2010-12-14
申请号：US12125975
申请日：2008-05-23
申请人： Haiwen Xi , Yang Li , Song S. Xue
发明人： Haiwen Xi , Yang Li , Song S. Xue
IPC分类号： G11C11/00
CPC分类号： H03K19/173 , G11C11/161 , G11C11/1673
摘要： Spin torque magnetic logic device having at least one input element and an output element. Current is applied through the input element(s), and the resulting resistance or voltage across the output element is measured. The input element(s) include a free layer and the output element includes a free layer that is electrically connected to the free layer of the input element. The free layers of the input element and the output element may be electrically connected via magnetostatic coupling, or may be physically coupled. In some embodiments, the output element may have more than one free layer.
摘要翻译：具有至少一个输入元件和输出元件的自旋扭矩磁逻辑器件。通过输入元件施加电流，并测量输出元件两端产生的电阻或电压。输入元件包括自由层，并且输出元件包括电连接到输入元件的自由层的自由层。输入元件和输出元件的自由层可以通过静磁耦合电连接，或者可以物理耦合。在一些实施例中，输出元件可以具有多于一个的自由层。

65. 发明授权

US07825397B2 Short bridge phase change memory cells 有权
标题翻译：短桥相变存储单元
公开(公告)号：US07825397B2
公开(公告)日：2010-11-02
申请号：US12125970
申请日：2008-05-23
申请人： Haiwen Xi , Song S. Xue
发明人： Haiwen Xi , Song S. Xue
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/1253 , H01L45/144
摘要： Random access memory cells having a short phase change bridge structure and methods of making the bridge structure via shadow deposition. The short bridge structure reduces the heating efficiency needed to switch the logic state of the memory cell. In one particular embodiment, the memory cell has a first electrode and a second electrode with a gap therebetween. The first electrode has an end at least partially non-orthogonal to the substrate and the second electrode has an end at least partially non-orthogonal to the substrate. A phase change material bridge extends over at least a portion of the first electrode, over at least a portion of the second electrode, and within the gap. An insulative material encompasses at least a portion of the phase change material bridge.
摘要翻译：具有短相变桥结构的随机存取存储单元和通过阴影沉积制造桥结构的方法。短桥结构降低了切换存储单元的逻辑状态所需的加热效率。在一个特定实施例中，存储单元具有第一电极和在其之间具有间隙的第二电极。第一电极具有至少部分地与衬底非正交的端部，并且第二电极具有至少部分地与衬底非正交的端部。相变材料桥在第一电极的至少一部分上延伸到第二电极的至少一部分上，并在间隙内延伸。绝缘材料包含相变材料桥的至少一部分。

66. 发明申请

US20090315088A1 FERROELECTRIC MEMORY USING MULTIFERROICS 失效
标题翻译：使用多媒体的电磁记忆
公开(公告)号：US20090315088A1
公开(公告)日：2009-12-24
申请号：US12144697
申请日：2008-06-24
申请人： Haiwen Xi , Wei Tian , Yang Li , Insik Jin , Song S. Xue
发明人： Haiwen Xi , Wei Tian , Yang Li , Insik Jin , Song S. Xue
IPC分类号： H01L29/00
CPC分类号： G11C11/22 , H01F10/22 , H01F10/24 , H01L29/78391
摘要： Ferroelectric memory using multiferroics is described. The multiferrroic memory includes a substrate having a source region, a drain region and a channel region separating the source region and the drain region. An electrically insulating layer is adjacent to the source region, drain region and channel region. A data storage cell having a composite multiferroic layer is adjacent to the electrically insulating layer. The electrically insulating layer separated the data storage cell form the channel region. A control gate electrode is adjacent to the data storage cell. The data storage cell separates at least a portion of the control gate electrode from the electrically insulating layer.
摘要翻译：描述了使用多铁性的铁电存储器。多层存储器包括具有源极区，漏极区和分离源极区和漏极区的沟道区的衬底。电绝缘层与源极区，漏极区和沟道区相邻。具有复合多铁层的数据存储单元与电绝缘层相邻。电绝缘层从通道区域分离数据存储单元。控制栅电极与数据存储单元相邻。数据存储单元将控制栅电极的至少一部分与电绝缘层分离。

67. 发明申请

US20090290411A1 WRITE VERIFY METHOD FOR RESISTIVE RANDOM ACCESS MEMORY 有权
标题翻译：用于电阻随机访问存储器的写作验证方法
公开(公告)号：US20090290411A1
公开(公告)日：2009-11-26
申请号：US12123647
申请日：2008-05-20
申请人： Haiwen Xi , Song S. Xue
发明人： Haiwen Xi , Song S. Xue
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5664 , G11C11/5685 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/0064 , G11C2013/0073 , G11C2211/5621 , G11C2213/31 , G11C2213/32
摘要： Write verify methods for resistance random access memory (RRAM) are disclosed. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state and setting a counter to zero. Then the method includes applying a forward resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance value less than a selected lower resistance limit value and adding one to the counter. This step is repeated until either the counter reaches a predetermined number or until the high resistance state resistance value is greater than the lower resistance limit value. The method also includes applying a reverse resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance values is greater than a selected upper resistance limit value and adding one to the counter. The reverse resetting voltage pulse has a second polarity being opposite the first polarity. This step is repeated until either the counter reaches a predetermined number or until all the high resistance state resistance value is less than the upper resistance limit value.
摘要翻译：公开了电阻随机存取存储器（RRAM）的写验证方法。所述方法包括在RRAM单元之间施加复位操作电压脉冲，以将RRAM单元的电阻从低电阻状态改变为高电阻状态，并将计数器设置为零。然后，该方法包括如果RRAM单元具有小于所选择的较低电阻极限值的高电阻状态电阻值并且将一个加到计数器上，则在RRAM单元之间施加正向复位电压脉冲。重复该步骤直到计数器达到预定数量，或者直到高电阻状态电阻值大于下限电阻值。该方法还包括如果RRAM单元具有高电阻状态电阻值大于所选上限电阻值并将一个加到计数器上，则在RRAM单元之间施加反向复位电压脉冲。反向复位电压脉冲具有与第一极性相反的第二极性。重复该步骤直到计数器达到预定数量，或者直到所有高电阻状态电阻值都小于上限电阻值。

68. 发明授权

US08659939B2 Spin-torque memory with unidirectional write scheme 有权
标题翻译：具有单向写入方案的自旋力矩存储器
公开(公告)号：US08659939B2
公开(公告)日：2014-02-25
申请号：US13530460
申请日：2012-06-22
申请人： Haiwen Xi , Dexin Wang , Dimitar V. Dimitrov , Paul E. Anderson , Song S. Xue
发明人： Haiwen Xi , Dexin Wang , Dimitar V. Dimitrov , Paul E. Anderson , Song S. Xue
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , B82Y25/00 , G01R33/093 , G01R33/1284 , G06T11/001 , G11C11/161 , G11C11/1675
摘要： Spin torque magnetic memory elements that have a pinned layer, two free layers, and a current-blocking insulating layer proximate to at least one of the free layers. The resistive state (e.g., low resistance or high resistance) of the memory elements is altered by passing electric current through the element in one direction. In other words, to change from a low resistance to a high resistance, the direction of electric current is the same as to change from a high resistance to a low resistance. The elements have a unidirectional write scheme.
摘要翻译：具有钉扎层，两个自由层和靠近至少一个自由层的电流阻挡绝缘层的自旋扭矩磁存储元件。存储元件的电阻状态（例如，低电阻或高电阻）通过在一个方向上通过元件的电流来改变。换句话说，为了从低电阻变为高电阻，电流的方向与从高电阻变为低电阻相同。这些元素具有单向写入方案。

69. 发明授权

US08659852B2 Write-once magentic junction memory array 有权
标题翻译：一次写入磁存储器阵列
公开(公告)号：US08659852B2
公开(公告)日：2014-02-25
申请号：US12106363
申请日：2008-04-21
申请人： Haiwen Xi , Song S. Xue
发明人： Haiwen Xi , Song S. Xue
IPC分类号： G11B5/33
CPC分类号： G11C11/1675 , G11C11/161 , G11C11/1673
摘要： A magnetic junction memory array and methods of using the same are described. The magnetic junction memory array includes a plurality of electrically conductive word lines extending in a first direction, a plurality of electrically conductive bit lines extending in a second direction and forming a cross-point array with the plurality of electrically conductive word lines, and a memory cell proximate to, at least selected, cross-points forming a magnetic junction memory array. Each memory cell includes a magnetic pinned layer electrically between a magnetic bit and an isolation transistor. The isolation transistor has a current source and a gate. The current source is electrically coupled to the cross-point bit line and the gate is electrically coupled to the cross-point word line. An electrically conductive cover layer is disposed on and in electrical communication with the magnetic bits.
摘要翻译：描述了磁结存储器阵列及其使用方法。磁结存储器阵列包括沿第一方向延伸的多个导电字线，沿第二方向延伸的多个导电位线，并与多个导电字线形成交叉点阵列，以及存储器靠近，至少选择的形成磁结存储器阵列的交叉点的单元。每个存储单元包括在磁性位和隔离晶体管之间电气的磁性固定层。隔离晶体管具有电流源和栅极。电流源电耦合到交叉点位线，并且栅极电耦合到交叉点字线。导电覆盖层设置在与磁头电气连接的位置上。

70. 发明授权

US08399908B2 Programmable metallization memory cells via selective channel forming 有权
标题翻译：可编程金属化存储单元通过选择性通道形成
公开(公告)号：US08399908B2
公开(公告)日：2013-03-19
申请号：US13348253
申请日：2012-01-11
申请人： Haiwen Xi , Ming Sun , Dexin Wang , Shuiyuan Huang , Michael Tang , Song S. Xue
发明人： Haiwen Xi , Ming Sun , Dexin Wang , Shuiyuan Huang , Michael Tang , Song S. Xue
IPC分类号： H01L29/66
CPC分类号： H01L45/085 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/1233 , H01L45/1246 , H01L45/1266 , H01L45/141 , H01L45/143 , H01L45/1625 , H01L45/1633 , H01L45/1658 , H01L45/1675
摘要： Methods for making a programmable metallization memory cell are disclosed.
摘要翻译：公开了制造可编程金属化存储单元的方法。

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