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    • 2. 发明授权
    • Write verify method for resistive random access memory
    • 电阻随机存取存储器的写验证方法
    • US08059450B2
    • 2011-11-15
    • US12899646
    • 2010-10-07
    • Haiwen XiSong S. Xue
    • Haiwen XiSong S. Xue
    • G11C11/00
    • G11C13/0069G11C11/5664G11C11/5685G11C13/0007G11C13/0014G11C13/0016G11C13/0064G11C2013/0073G11C2211/5621G11C2213/31G11C2213/32
    • Write verify methods for resistance random access memory (RRAM) are provided. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state. Then the method includes applying a forward resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance value less than a selected lower resistance limit value. This step is repeated until the high resistance state resistance value is greater than the lower resistance limit value. The method also includes applying a reverse resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance values is greater than a selected upper resistance limit value. The reverse resetting voltage pulse has a second polarity being opposite the first polarity. This step is repeated until all the high resistance state resistance value is less than the upper resistance limit value.
    • 提供了电阻随机存取存储器(RRAM)的写验证方法。 所述方法包括在RRAM单元之间施加复位操作电压脉冲,以将RRAM单元的电阻从低电阻状态改变为高电阻状态。 然后,该方法包括如果RRAM单元具有小于所选择的较低电阻极限值的高电阻状态电阻值,则在RRAM单元之间施加正向复位电压脉冲。 重复该步骤直到高电阻状态电阻值大于下限电阻值。 该方法还包括如果RRAM单元具有大于所选上限电阻值的高电阻状态电阻值,则跨越RRAM单元施加反向复位电压脉冲。 反向复位电压脉冲具有与第一极性相反的第二极性。 重复该步骤,直到所有高电阻状态电阻值小于上限电阻值。
    • 7. 发明授权
    • Write verify method for resistive random access memory
    • 电阻随机存取存储器的写验证方法
    • US07826248B2
    • 2010-11-02
    • US12123647
    • 2008-05-20
    • Haiwen XiSong S. Xue
    • Haiwen XiSong S. Xue
    • G11C11/00
    • G11C13/0069G11C11/5664G11C11/5685G11C13/0007G11C13/0014G11C13/0016G11C13/0064G11C2013/0073G11C2211/5621G11C2213/31G11C2213/32
    • Write verify methods for resistance random access memory (RRAM) are provided. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state and setting a counter to zero. Then the method includes applying a forward resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance value less than a selected lower resistance limit value and adding one to the counter. This step is repeated until either the counter reaches a predetermined number or until the high resistance state resistance value is greater than the lower resistance limit value. The method also includes applying a reverse resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance values is greater than a selected upper resistance limit value and adding one to the counter. The reverse resetting voltage pulse has a second polarity being opposite the first polarity. This step is repeated until either the counter reaches a predetermined number or until all the high resistance state resistance value is less than the upper resistance limit value.
    • 提供了电阻随机存取存储器(RRAM)的写验证方法。 所述方法包括在RRAM单元之间施加复位操作电压脉冲,以将RRAM单元的电阻从低电阻状态改变为高电阻状态,并将计数器设置为零。 然后,该方法包括如果RRAM单元具有小于所选择的较低电阻极限值的高电阻状态电阻值并且将一个加到计数器上,则在RRAM单元之间施加正向复位电压脉冲。 重复该步骤直到计数器达到预定数量,或者直到高电阻状态电阻值大于下限电阻值。 该方法还包括如果RRAM单元具有高电阻状态电阻值大于所选上限电阻值并将一个加到计数器上,则在RRAM单元之间施加反向复位电压脉冲。 反向复位电压脉冲具有与第一极性相反的第二极性。 重复该步骤直到计数器达到预定数量,或者直到所有高电阻状态电阻值都小于上限电阻值。
    • 10. 发明申请
    • MAGENTIC JUNCTION MEMORY ARRAY
    • 磁性连接记忆阵列
    • US20090262467A1
    • 2009-10-22
    • US12106363
    • 2008-04-21
    • Haiwen XiSong S. Xue
    • Haiwen XiSong S. Xue
    • G11B5/33
    • G11C11/1675G11C11/161G11C11/1673
    • A magnetic junction memory array and methods of using the same are described. The magnetic junction memory array includes a plurality of electrically conductive word lines extending in a first direction, a plurality of electrically conductive bit lines extending in a second direction and forming a cross-point array with the plurality of electrically conductive word lines, and a memory cell proximate to, at least selected, cross-points forming a magnetic junction memory array. Each memory cell includes a magnetic pinned layer electrically between a magnetic bit and an isolation transistor. The isolation transistor has a current source and a gate. The current source is electrically coupled to the cross-point bit line and the gate is electrically coupled to the cross-point word line. An electrically conductive cover layer is disposed on and in electrical communication with the magnetic bits.
    • 描述了磁结存储器阵列及其使用方法。 磁结存储器阵列包括沿第一方向延伸的多个导电字线,沿第二方向延伸的多个导电位线,并与多个导电字线形成交叉点阵列,以及存储器 靠近,至少选择的形成磁结存储器阵列的交叉点的单元。 每个存储单元包括在磁性位和隔离晶体管之间电气的磁性固定层。 隔离晶体管具有电流源和栅极。 电流源电耦合到交叉点位线,并且栅极电耦合到交叉点字线。 导电覆盖层设置在与磁头电气连接的位置上。