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1. 发明申请

US20100054026A1 MEMORY WITH SEPARATE READ AND WRITE PATHS 有权
标题翻译：具有单独读取和写入数据的存储器
公开(公告)号：US20100054026A1
公开(公告)日：2010-03-04
申请号：US12198416
申请日：2008-08-26
申请人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
发明人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line and a magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line. A write current passing through the giant magnetoresistance cell switches the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell. The magnetic tunnel junction data cell is read by a read current passing though the magnetic tunnel junction data cell.
摘要翻译：存储单元包括电耦合在写位线和写入源线之间的电磁耦合单元和电耦合在读取位线和读取源极线之间的磁性隧道结数据单元的巨磁电阻单元。通过巨磁电阻单元的写入电流将巨磁阻单元切换到高电阻状态和低电阻状态之间。磁隧道结数据单元被配置为通过与巨磁阻单元的静磁耦合在高电阻状态和低电阻状态之间切换。磁隧道结数据单元由通过磁性隧道结数据单元的读取电流读取。

2. 发明授权

US08400823B2 Memory with separate read and write paths 有权
标题翻译：内存具有单独的读写路径
公开(公告)号：US08400823B2
公开(公告)日：2013-03-19
申请号：US12774016
申请日：2010-05-05
申请人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
发明人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
IPC分类号： G11C11/00
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.
摘要翻译：存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。磁性隧道结数据单元电耦合在读取位线和读取源极线之间。磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。写入电流通过巨磁电阻单元，以将巨磁阻单元切换到高电阻状态和低电阻状态之间。磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

3. 发明申请

US20110090733A1 MEMORY WITH SEPARATE READ AND WRITE PATHS 有权
标题翻译：具有单独读取和写入数据的存储器
公开(公告)号：US20110090733A1
公开(公告)日：2011-04-21
申请号：US12974679
申请日：2010-12-21
申请人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
发明人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
IPC分类号： G11C11/15
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.
摘要翻译：存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。磁性隧道结数据单元电耦合在读取位线和读取源极线之间。磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。写入电流通过巨磁电阻单元，以在高电阻状态和低电阻状态之间切换巨磁电阻单元。磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

4. 发明授权

US07881098B2 Memory with separate read and write paths 有权
标题翻译：内存具有单独的读写路径
公开(公告)号：US07881098B2
公开(公告)日：2011-02-01
申请号：US12198416
申请日：2008-08-26
申请人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
发明人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
IPC分类号： G11C11/00
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line and a magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line. A write current passing through the giant magnetoresistance cell switches the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell. The magnetic tunnel junction data cell is read by a read current passing though the magnetic tunnel junction data cell.
摘要翻译：存储单元包括电耦合在写位线和写入源线之间的电磁耦合单元和电耦合在读取位线和读取源极线之间的磁性隧道结数据单元的巨磁电阻单元。通过巨磁电阻单元的写入电流将巨磁阻单元切换到高电阻状态和低电阻状态之间。磁隧道结数据单元被配置为通过与巨磁阻单元的静磁耦合在高电阻状态和低电阻状态之间切换。磁隧道结数据单元由通过磁性隧道结数据单元的读取电流读取。

5. 发明申请

US20100208513A1 MEMORY WITH SEPARATE READ AND WRITE PATHS 有权
标题翻译：具有单独读取和写入数据的存储器
公开(公告)号：US20100208513A1
公开(公告)日：2010-08-19
申请号：US12774016
申请日：2010-05-05
申请人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
发明人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.
摘要翻译：存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。磁性隧道结数据单元电耦合在读取位线和读取源极线之间。磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。写入电流通过巨磁电阻单元，以将巨磁阻单元切换到高电阻状态和低电阻状态之间。磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

6. 发明授权

US08422278B2 Memory with separate read and write paths 有权
标题翻译：内存具有单独的读写路径
公开(公告)号：US08422278B2
公开(公告)日：2013-04-16
申请号：US12974679
申请日：2010-12-21
申请人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
发明人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
IPC分类号： G11C11/15
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.
摘要翻译：存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。磁性隧道结数据单元电耦合在读取位线和读取源极线之间。磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。写入电流通过巨磁电阻单元，以在高电阻状态和低电阻状态之间切换巨磁电阻单元。磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

7. 发明申请

US20100057984A1 MEMORY HIERARCHY CONTAINING ONLY NON-VOLATILE CACHE 审中-公开
标题翻译：仅包含非易失性高速缓存的内存分层
公开(公告)号：US20100057984A1
公开(公告)日：2010-03-04
申请号：US12198513
申请日：2008-08-26
申请人： Yiran Chen , Hai Li , Hongyue Liu , Haiwen Xi , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Haiwen Xi , Song S. Xue
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0804 , G06F12/0868 , G06F12/0897 , G06F2212/2022 , G06F2212/2024 , G06F2212/222
摘要： A storage system that includes non-volatile main memory; non-volatile read cache; non-volatile write cache; and a data path operably coupled between the non-volatile write cache and the non-volatile read cache, wherein the storage system does not include any volatile cache and methods for retrieving and writing data throughout this memory hierarchy system.
摘要翻译：一种包含非易失性主存储器的存储系统; 非易失性读取缓存; 非易失性写缓存; 以及可操作地耦合在所述非易失性写入高速缓存和所述非易失性读取高速缓存之间的数据路径，其中所述存储系统不包括用于在所述存储器层级系统中检索和写入数据的任何易失性高速缓存和方法。

8. 发明授权

US08766230B2 Non-volatile multi-bit memory with programmable capacitance 失效
标题翻译：具有可编程电容的非易失性多位存储器
公开(公告)号：US08766230B2
公开(公告)日：2014-07-01
申请号：US12857717
申请日：2010-08-17
申请人： Xuguang Wang , Shuiyuan Huang , Dimitar V. Dimitrov , Michael Xuefei Tang , Song S. Xue
发明人： Xuguang Wang , Shuiyuan Huang , Dimitar V. Dimitrov , Michael Xuefei Tang , Song S. Xue
IPC分类号： H01L45/00
CPC分类号： H01L45/085 , G11C16/0475 , H01L45/1206 , H01L45/1266 , H01L45/143 , H01L45/1658
摘要： Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region; and a gate stack structure over the substrate and between the source region and drain region. The gate stack structure includes a first solid electrolyte cell and a second solid electrolyte cell. The solid electrolyte cells having a capacitance that is controllable between at least two states. A gate contact layer is electrically coupled to a voltage source. The first solid electrolyte cell and the second solid electrolyte cell separate the gate contact layer from the substrate.
摘要翻译：公开了具有可编程电容的非易失性多位存储器。说明性的数据存储单元包括一个包括源极区和漏极区的衬底; 以及在衬底上以及在源极区和漏极区之间的栅叠层结构。栅堆叠结构包括第一固体电解质电池和第二固体电解质电池。固体电解质电池具有在至少两个状态之间可控制的电容。栅极接触层电耦合到电压源。第一固体电解质电池和第二固体电解质电池将栅极接触层与基板分离。

9. 发明授权

US07786463B2 Non-volatile multi-bit memory with programmable capacitance 有权
标题翻译：带可编程电容的非易失性多位存储器
公开(公告)号：US07786463B2
公开(公告)日：2010-08-31
申请号：US12123685
申请日：2008-05-20
申请人： Xuguang Wang , Shuiyuan Huang , Dimitar V. Dimitrov , Michael Xuefei Tang , Song S. Xue
发明人： Xuguang Wang , Shuiyuan Huang , Dimitar V. Dimitrov , Michael Xuefei Tang , Song S. Xue
IPC分类号： H01L45/00
CPC分类号： H01L45/085 , G11C16/0475 , H01L45/1206 , H01L45/1266 , H01L45/143 , H01L45/1658
摘要： Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A first solid electrolyte cell is over the insulating layer and has a capacitance that is controllable between at least two states and is proximate the source region. A second solid electrolyte cell is over the insulating layer and has a capacitance or resistance that is controllable between at least two states and is proximate the drain region. An insulating element isolates the first solid electrolyte cell from the second solid electrolyte cell. A first anode is electrically coupled to the first solid electrolyte cell. The first solid electrolyte cell is between the anode and the insulating layer. A second anode is electrically coupled to the second solid electrolyte cell. The second solid electrolyte cell is between the anode and the insulating layer. A gate contact layer is over the substrate and between the source region and drain region and in electrical connection with the first anode and the second anode. The gate contact layer is electrically coupled to a voltage source.
摘要翻译：公开了具有可编程电容的非易失性多位存储器。说明性数据存储单元包括包括源极区和漏极区的衬底。第一绝缘层在衬底上。第一固体电解质电池在绝缘层之上并且具有在至少两个状态之间可控并且在源极区附近的电容。第二固体电解质电池在绝缘层之上，并且具有在至少两个状态之间可控的并且在漏极区附近的电容或电阻。绝缘元件将第一固体电解质电池与第二固体电解质电池隔离。第一阳极电耦合到第一固体电解质电池。第一固体电解质电池在阳极和绝缘层之间。第二阳极电耦合到第二固体电解质电池。第二固体电解质电池在阳极和绝缘层之间。栅极接触层在衬底上并且在源极区域和漏极区域之间并且与第一阳极和第二阳极电连接。栅极接触层电耦合到电压源。

10. 发明授权

US07977722B2 Non-volatile memory with programmable capacitance 有权
标题翻译：具有可编程电容的非易失性存储器
公开(公告)号：US07977722B2
公开(公告)日：2011-07-12
申请号：US12123662
申请日：2008-05-20
申请人： Xuguang Wang , Shuiyuan Huang , Dimitar V. Dimitrov , Michael Xuefei Tang , Song S. Xue
发明人： Xuguang Wang , Shuiyuan Huang , Dimitar V. Dimitrov , Michael Xuefei Tang , Song S. Xue
IPC分类号： H01L29/92
CPC分类号： G11C13/0069 , G11C11/5614 , G11C13/0011 , G11C2213/53 , H01L29/42324 , H01L29/7881
摘要： Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed.
摘要翻译：公开了具有可编程电容的非易失性存储器。说明性数据存储单元包括包括源极区和漏极区的衬底。第一绝缘层在衬底上。第二绝缘层在衬底上并且在源极区和漏极区之间。固体电解质层位于第一绝缘层和第二绝缘层之间。固体电解质层具有在至少两种状态之间可控的电容。第一电极电耦合到固体电解质层的第一侧并且电耦合到电压源。第二电极电耦合到固体电解质层的第二侧并且电耦合到电压源。还公开了多位存储器单元。

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