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1. 发明申请

US20100054026A1 MEMORY WITH SEPARATE READ AND WRITE PATHS 有权
标题翻译：具有单独读取和写入数据的存储器
公开(公告)号：US20100054026A1
公开(公告)日：2010-03-04
申请号：US12198416
申请日：2008-08-26
申请人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
发明人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line and a magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line. A write current passing through the giant magnetoresistance cell switches the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell. The magnetic tunnel junction data cell is read by a read current passing though the magnetic tunnel junction data cell.
摘要翻译：存储单元包括电耦合在写位线和写入源线之间的电磁耦合单元和电耦合在读取位线和读取源极线之间的磁性隧道结数据单元的巨磁电阻单元。通过巨磁电阻单元的写入电流将巨磁阻单元切换到高电阻状态和低电阻状态之间。磁隧道结数据单元被配置为通过与巨磁阻单元的静磁耦合在高电阻状态和低电阻状态之间切换。磁隧道结数据单元由通过磁性隧道结数据单元的读取电流读取。

2. 发明申请

US20100208513A1 MEMORY WITH SEPARATE READ AND WRITE PATHS 有权
标题翻译：具有单独读取和写入数据的存储器
公开(公告)号：US20100208513A1
公开(公告)日：2010-08-19
申请号：US12774016
申请日：2010-05-05
申请人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
发明人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.
摘要翻译：存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。磁性隧道结数据单元电耦合在读取位线和读取源极线之间。磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。写入电流通过巨磁电阻单元，以将巨磁阻单元切换到高电阻状态和低电阻状态之间。磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

3. 发明授权

US08422278B2 Memory with separate read and write paths 有权
标题翻译：内存具有单独的读写路径
公开(公告)号：US08422278B2
公开(公告)日：2013-04-16
申请号：US12974679
申请日：2010-12-21
申请人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
发明人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
IPC分类号： G11C11/15
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.
摘要翻译：存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。磁性隧道结数据单元电耦合在读取位线和读取源极线之间。磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。写入电流通过巨磁电阻单元，以在高电阻状态和低电阻状态之间切换巨磁电阻单元。磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

4. 发明授权

US08400823B2 Memory with separate read and write paths 有权
标题翻译：内存具有单独的读写路径
公开(公告)号：US08400823B2
公开(公告)日：2013-03-19
申请号：US12774016
申请日：2010-05-05
申请人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
发明人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
IPC分类号： G11C11/00
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.
摘要翻译：存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。磁性隧道结数据单元电耦合在读取位线和读取源极线之间。磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。写入电流通过巨磁电阻单元，以将巨磁阻单元切换到高电阻状态和低电阻状态之间。磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

5. 发明申请

US20110090733A1 MEMORY WITH SEPARATE READ AND WRITE PATHS 有权
标题翻译：具有单独读取和写入数据的存储器
公开(公告)号：US20110090733A1
公开(公告)日：2011-04-21
申请号：US12974679
申请日：2010-12-21
申请人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
发明人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
IPC分类号： G11C11/15
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.
摘要翻译：存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。磁性隧道结数据单元电耦合在读取位线和读取源极线之间。磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。写入电流通过巨磁电阻单元，以在高电阻状态和低电阻状态之间切换巨磁电阻单元。磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

6. 发明授权

US07881098B2 Memory with separate read and write paths 有权
标题翻译：内存具有单独的读写路径
公开(公告)号：US07881098B2
公开(公告)日：2011-02-01
申请号：US12198416
申请日：2008-08-26
申请人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
发明人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
IPC分类号： G11C11/00
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line and a magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line. A write current passing through the giant magnetoresistance cell switches the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell. The magnetic tunnel junction data cell is read by a read current passing though the magnetic tunnel junction data cell.
摘要翻译：存储单元包括电耦合在写位线和写入源线之间的电磁耦合单元和电耦合在读取位线和读取源极线之间的磁性隧道结数据单元的巨磁电阻单元。通过巨磁电阻单元的写入电流将巨磁阻单元切换到高电阻状态和低电阻状态之间。磁隧道结数据单元被配置为通过与巨磁阻单元的静磁耦合在高电阻状态和低电阻状态之间切换。磁隧道结数据单元由通过磁性隧道结数据单元的读取电流读取。

7. 发明申请

US20100118579A1 Nand Based Resistive Sense Memory Cell Architecture 有权
标题翻译：基于Nand的电阻感知存储器单元架构
公开(公告)号：US20100118579A1
公开(公告)日：2010-05-13
申请号：US12269656
申请日：2008-11-12
申请人： Harry Hongyue Liu , Haiwen Xi , Antoine Khoueir , Song Xue
发明人： Harry Hongyue Liu , Haiwen Xi , Antoine Khoueir , Song Xue
IPC分类号： G11C5/02 , G11C11/00 , G11C8/00 , G11C11/34
CPC分类号： H01L27/24 , G11C11/1659 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/34 , G11C2213/75 , H01L27/228
摘要： Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.
摘要翻译：各种实施例涉及一种包括具有布置在NAND块中的非易失性存储器单元的半导体存储器阵列的装置。每个单元电池包括与开关元件并联连接的电阻感测元件。电阻感测元件串联连接以形成第一串行路径，并且开关元件串联连接以形成平行于第一串行路径的第二串行路径。每个电阻感测元件通过具有在所述元件之间基本上垂直延伸的部分的曲折导电路径串联连接到块中的相邻电阻感测元件，以提供对其的操作隔离。

8. 发明授权

US08363442B2 NAND based resistive sense memory cell architecture 有权
标题翻译：基于NAND的电阻式读写单元架构
公开(公告)号：US08363442B2
公开(公告)日：2013-01-29
申请号：US12903716
申请日：2010-10-13
申请人： Harry Hongyue Liu , Haiwen Xi , Antoine Khoueir , Song Xue
发明人： Harry Hongyue Liu , Haiwen Xi , Antoine Khoueir , Song Xue
IPC分类号： G11C5/02
CPC分类号： H01L27/24 , G11C11/1659 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/34 , G11C2213/75 , H01L27/228
摘要： Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.
摘要翻译：各种实施例涉及一种包括具有布置在NAND块中的非易失性存储器单元的半导体存储器阵列的装置。每个单元电池包括与开关元件并联连接的电阻感测元件。电阻感测元件串联连接以形成第一串行路径，并且开关元件串联连接以形成平行于第一串行路径的第二串行路径。每个电阻感测元件通过具有在所述元件之间基本上垂直延伸的部分的曲折导电路径串联连接到块中的相邻电阻感测元件，以提供对其的操作隔离。

9. 发明申请

US20110032749A1 NAND Based Resistive Sense Memory Cell Architecture 有权
标题翻译：基于NAND的电阻式感应存储器单元架构
公开(公告)号：US20110032749A1
公开(公告)日：2011-02-10
申请号：US12903716
申请日：2010-10-13
申请人： Harry Hongyue Liu , Haiwen Xi , Antoine Khoueir , Song Xue
发明人： Harry Hongyue Liu , Haiwen Xi , Antoine Khoueir , Song Xue
IPC分类号： G11C11/34 , H01L45/00
CPC分类号： H01L27/24 , G11C11/1659 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/34 , G11C2213/75 , H01L27/228
摘要： Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.
摘要翻译：各种实施例涉及一种包括具有布置在NAND块中的非易失性存储器单元的半导体存储器阵列的装置。每个单元电池包括与开关元件并联连接的电阻感测元件。电阻感测元件串联连接以形成第一串行路径，并且开关元件串联连接以形成平行于第一串行路径的第二串行路径。每个电阻感测元件通过具有在所述元件之间基本上垂直延伸的部分的曲折导电路径串联连接到块中的相邻电阻感测元件，以提供对其的操作隔离。

10. 发明授权

US07830693B2 NAND based resistive sense memory cell architecture 有权
标题翻译：基于NAND的电阻式读写单元架构
公开(公告)号：US07830693B2
公开(公告)日：2010-11-09
申请号：US12269656
申请日：2008-11-12
申请人： Harry Hongyue Liu , Haiwen Xi , Antoine Khoueir , Song Xue
发明人： Harry Hongyue Liu , Haiwen Xi , Antoine Khoueir , Song Xue
IPC分类号： G11C5/02
CPC分类号： H01L27/24 , G11C11/1659 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/34 , G11C2213/75 , H01L27/228
摘要： Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.
摘要翻译：各种实施例涉及一种包括具有布置在NAND块中的非易失性存储器单元的半导体存储器阵列的装置。每个单元电池包括与开关元件并联连接的电阻感测元件。电阻感测元件串联连接以形成第一串行路径，并且开关元件串联连接以形成平行于第一串行路径的第二串行路径。每个电阻感测元件通过具有在所述元件之间基本上垂直延伸的部分的曲折导电路径串联连接到块中的相邻电阻感测元件，以提供对其的操作隔离。

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