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61. 发明授权

US07749327B2 Methods for treating surfaces 失效
标题翻译：表面处理方法
公开(公告)号：US07749327B2
公开(公告)日：2010-07-06
申请号：US11933770
申请日：2007-11-01
申请人： Nishant Sinha , Gurtej S. Sandhu
发明人： Nishant Sinha , Gurtej S. Sandhu
IPC分类号： B08B3/00 , B08B3/04
CPC分类号： B08B3/10 , B08B7/02 , B24C3/322 , B24C7/0007 , H01L21/02052 , H01L21/02057 , H01L21/67051
摘要： Some embodiments include methods for treating surfaces. Beads and/or other insolubles may be dispersed within a liquid carrier to form a dispersion. A transfer layer may be formed across a surface. The dispersion may be directed toward the transfer layer, and the insolubles may impact the transfer layer. The impacting may generate force in the transfer layer, and such force may be transferred through the transfer layer to the surface. The surface may be a surface of a semiconductor substrate, and the force may be utilized to sweep contaminants from the semiconductor substrate surface. The transfer layer may be a liquid, and in some embodiments may be a cleaning solution.
摘要翻译：一些实施方案包括用于处理表面的方法。珠和/或其他不溶物可以分散在液体载体中以形成分散体。可以跨越表面形成转印层。分散体可以指向转移层，并且不溶物可能影响转移层。冲击可能在转移层中产生力，并且这种力可以通过转移层转移到表面。表面可以是半导体衬底的表面，并且该力可用于从半导体衬底表面扫除污染物。转移层可以是液体，并且在一些实施方案中可以是清洁溶液。

62. 发明申请

US20100144153A1 Methods of Fabricating Substrates 有权
标题翻译：制造基板的方法
公开(公告)号：US20100144153A1
公开(公告)日：2010-06-10
申请号：US12328464
申请日：2008-12-04
申请人： Scott Sills , Gurtej S. Sandhu , Anton deVilliers
发明人： Scott Sills , Gurtej S. Sandhu , Anton deVilliers
IPC分类号： H01L21/027
CPC分类号： H01L21/31138 , G03F7/0035 , H01L21/0273 , H01L21/0337 , H01L21/0338
摘要： A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate with one another and are spaced relative one another. Width of the spaced second features is laterally trimmed to a greater degree than any lateral trimming of width of the spaced first features while laterally trimming width of the spaced second features. After laterally trimming of the second features, spacers are formed on sidewalls of the spaced first features and on sidewalls of the spaced second features. The spacers are of some different composition from that of the spaced first features and from that of the spaced second features. After forming the spacers, the spaced first features and the spaced second features are removed from the substrate. The substrate is processed through a mask pattern comprising the spacers. Other embodiments are disclosed.
摘要翻译：一种制造衬底的方法包括在衬底上形成间隔开的第一特征和间隔开的第二特征。第一和第二特征彼此交替并彼此间隔开。间隔开的第二特征的宽度被横向修剪到比间隔开的第一特征的宽度的任何横向修剪更大的程度，同时横向修剪间隔开的第二特征的宽度。在第二特征的横向修剪之后，间隔物形成在间隔开的第一特征的侧壁上并且在间隔开的第二特征的侧壁上。间隔物与间隔开的第一特征和间隔开的第二特征的间隔物具有不同的组成。在形成间隔物之后，从衬底去除间隔开的第一特征和间隔开的第二特征。通过包括间隔物的掩模图案处理衬底。公开了其他实施例。

63. 发明申请

US20100144150A1 Methods of Fabricating Substrates 有权
标题翻译：制造基板的方法
公开(公告)号：US20100144150A1
公开(公告)日：2010-06-10
申请号：US12328435
申请日：2008-12-04
申请人： Scott Sills , Gurtej S. Sandhu , Anton de Villiers
发明人： Scott Sills , Gurtej S. Sandhu , Anton de Villiers
IPC分类号： H01L21/311
CPC分类号： H01L21/31138 , H01L21/0273 , H01L21/0337 , H01L21/0338
摘要： A method of fabricating a substrate includes forming first and second spaced features over a substrate. The first spaced features have elevationally outermost regions which are different in composition from elevationally outermost regions of the second spaced features. The first and second spaced features alternate with one another. Every other first feature is removed from the substrate and pairs of immediately adjacent second features are formed which alternate with individual of remaining of the first features. After such act of removing, the substrate is processed through a mask pattern comprising the pairs of immediately adjacent second features which alternate with individual of the remaining of the first features. Other embodiments are disclosed.
摘要翻译：一种制造衬底的方法包括在衬底上形成第一和第二间隔的特征。第一间隔的特征具有与第二间隔特征的垂直最外区域不同的高度最外的区域。第一和第二间隔的特征彼此交替。每个其他第一特征从衬底移除，并且形成直接相邻的第二特征对，其与第一特征的剩余部分的个体交替。在这样的去除动作之后，通过掩模图案来处理衬底，该掩模图案包括与第一特征剩余部分的个体交替的紧邻的第二特征对。公开了其他实施例。

64. 发明申请

US20100129980A1 Methods Of Forming Diodes 有权
标题翻译：形成二极管的方法
公开(公告)号：US20100129980A1
公开(公告)日：2010-05-27
申请号：US12323978
申请日：2008-11-26
申请人： Gurtej S. Sandhu , Bhaskar Srinivasan
发明人： Gurtej S. Sandhu , Bhaskar Srinivasan
IPC分类号： H01L21/329
CPC分类号： H01L21/04 , H01L27/1021 , H01L27/2418 , H01L29/1606 , H01L45/00
摘要： Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.
摘要翻译：一些实施例包括形成二极管的方法。可以在第一导电材料上形成堆叠。堆叠可以按升序包括牺牲材料，至少一种电介质材料和第二导电材料。间隔物可以沿着堆叠的相对侧壁形成，然后可以去除整个牺牲材料以在第一导电材料和至少一个电介质材料之间留下间隙。在形成二极管的一些实施例中，可以在第一导电材料上形成层，其中包含支撑体的层散布在牺牲材料中。可以在该层上形成至少一种介电材料，并且可以在该至少一种电介质材料的上方形成第二导电材料。然后可以去除整个牺牲材料。

65. 发明授权

US07723009B2 Topography based patterning 有权
标题翻译：地形图案
公开(公告)号：US07723009B2
公开(公告)日：2010-05-25
申请号：US11445907
申请日：2006-06-02
申请人： Gurtej S. Sandhu , Steve Kramer
发明人： Gurtej S. Sandhu , Steve Kramer
IPC分类号： G03F7/00 , G03F7/004
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/0338 , H01L21/3081 , H01L21/3086 , H01L21/3088
摘要： A mask having features formed by self-organizing material, such as diblock copolymers, is formed on a partially fabricated integrated circuit. Initially, a copolymer template, or seed layer, is formed on the surface of the partially fabricated integrated circuit. To form the seed layer, diblock copolymers, composed of two immiscible blocks, are deposited in the space between copolymer alignment guides. The copolymers are made to self-organize, with the guides guiding the self-organization and with each block aggregating with other blocks of the same type, thereby forming the seed layer. Next, additional, supplemental diblock copolymers are deposited over the seed layer. The copolymers in the seed layer guide self-organization of the supplemental copolymers, thereby vertically extending the pattern formed by the copolymers in the seed layer. Block species are subsequently selectively removed to form a pattern of voids defined by the remaining block species, which form a mask that can be used to pattern an underlying substrate. The supplemental copolymers augment the height of the copolymers in the seed layer, thereby facilitating the use of the copolymers for patterning the underlying substrate.
摘要翻译：在部分制造的集成电路上形成具有由诸如二嵌段共聚物之类的自组织材料形成的特征的掩模。最初，在部分制造的集成电路的表面上形成共聚物模板或种子层。为了形成种子层，由共混物对准引导件之间的空间中沉积由两个不混溶的嵌段组成的二嵌段共聚物。使共聚物自组织，引导引导自组织，每个块与相同类型的其它嵌段聚集，从而形成种子层。接下来，在种子层上沉积另外的补充二嵌段共聚物。种子层中的共聚物引导辅助共聚物的自组织，从而在种子层中垂直延伸由共聚物形成的图案。随后选择性地去除块物质以形成由剩余的嵌段物质限定的空隙图案，其形成可用于对下面的基底进行图案化的掩模。补充共聚物增加了种子层中共聚物的高度，从而有利于共聚物用于图案化下面的底物。

66. 发明申请

US20090302322A1 Method of Forming a Thin Film Transistor 审中-公开
公开(公告)号：US20090302322A1
公开(公告)日：2009-12-10
申请号：US12492991
申请日：2009-06-26
申请人： Gurtej S. Sandhu , Shubneesh Batra , Pierre C. Fazan
发明人： Gurtej S. Sandhu , Shubneesh Batra , Pierre C. Fazan
IPC分类号： H01L29/786 , H01L21/20
CPC分类号： H01L29/78678 , H01L27/1214 , H01L27/127 , H01L29/04 , H01L29/6675 , H01L29/66757 , H01L29/66765 , H01L29/78672 , H01L29/78675
摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.

67. 发明授权

US07629024B2 Methods of forming particle-containing materials 失效
标题翻译：形成含颗粒材料的方法
公开(公告)号：US07629024B2
公开(公告)日：2009-12-08
申请号：US11486522
申请日：2006-07-13
申请人： Garo J. Derderian , Gurtej S. Sandhu
发明人： Garo J. Derderian , Gurtej S. Sandhu
IPC分类号： B05D1/12 , H01L21/471
CPC分类号： H01L21/76838 , C23C16/45525 , C23C16/45555 , H01L21/02126 , H01L21/02164 , H01L21/0226 , H01L21/0228 , H01L21/288 , H01L21/3141 , H01L21/3146 , H01L21/31608 , H01L21/31633 , H01L21/76829 , H01L21/76837 , Y10S438/962 , Y10S438/964 , Y10T428/12493 , Y10T428/12528 , Y10T428/12576 , Y10T428/12806 , Y10T428/1284
摘要： The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials. One aspect of the invention includes a method in which a first monolayer is formed across at least a portion of a semiconductor substrate, particles are adhered to the first monolayer, and a second monolayer is formed over the particles. Another aspect of the invention includes a construction containing a semiconductor substrate and a particle-impregnated conductive material over at least a portion of the semiconductor substrate. The particle-impregnated conductive material can include tungsten-containing particles within a layer which includes tantalum or tungsten.
摘要翻译：本发明包括形成含颗粒材料的方法，还包括包含含颗粒的材料的半导体结构。本发明的一个方面包括一种方法，其中在半导体衬底的至少一部分上形成第一单层，颗粒粘附到第一单层，并且在颗粒上方形成第二单层。本发明的另一方面包括在半导体衬底的至少一部分上包含半导体衬底和含有颗粒的导电材料的结构。颗粒浸渍的导电材料可以包括在包括钽或钨的层内的含钨颗粒。

68. 发明申请

US20090263962A1 NON-VOLATILE MEMORY CELL DEVICE AND METHODS 有权
标题翻译：非易失性记忆细胞装置及方法
公开(公告)号：US20090263962A1
公开(公告)日：2009-10-22
申请号：US12496437
申请日：2009-07-01
申请人： Gurtej S. Sandhu , Kirk D. Prall
发明人： Gurtej S. Sandhu , Kirk D. Prall
IPC分类号： H01L21/28 , H01L21/311
CPC分类号： H01L29/7881 , B82Y10/00 , G11C16/0408 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/513
摘要： A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielectric layer. To form sidewalls of the memory cell, a portion of the intergate dielectric layer and a portion of the second dielectric layer are removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the second dielectric layer and the nanodots can be removed with an isotropic etch selective to the second dielectric layer.
摘要翻译：一种制造存储单元的方法，包括在第一介电层上形成纳米点，并在纳米点上形成第二介电层，其中第二介电层包裹纳米点。此外，在第二介电层上形成隔间电介质层。为了形成存储器单元的侧壁，间隔电介质层的一部分和第二电介质层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。在侧壁上形成间隔层以覆盖已经沉积纳米点的位置，并且可以用对第二介电层选择性的各向同性蚀刻去除第二介电层和纳米点的剩余部分。

69. 发明授权

US07598021B2 High resolution printing technique 失效
标题翻译：高分辨率打印技术
公开(公告)号：US07598021B2
公开(公告)日：2009-10-06
申请号：US11252465
申请日：2005-10-17
申请人： Gurtej S. Sandhu
发明人： Gurtej S. Sandhu
IPC分类号： G03F7/20
CPC分类号： H01L21/3088 , B82Y10/00 , G03F7/70383 , G11B9/1436 , G11B9/149 , G11B2005/0021 , H01L21/0337 , H01L21/3086
摘要： A pattern having exceptionally small features is printed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern is printed using an array of probes, each probe having: 1) a photocatalytic nanodot at its tip; and 2) an individually controlled light source. The surface of the partially fabricated integrated circuit comprises a photochemically active species. The active species undergoes a chemical change when contacted by the nanodot, when the nanodot is illuminated by light. To print a pattern, each probe raster-scans its associated nanodot across the surface of the partially fabricated integrated circuit. When the nanodot reaches a desired location, the nanodot is illuminated by the light source, catalyzing a change in the reactive species and, thus, printing at that location. Subsequently, reacted or unreacted species are selectively removed, thereby forming a mask pattern over the partially fabricated integrated circuit. The minimum size of the features in the pattern is determined by the size of the nanodot and can be very small, e.g., having critical dimensions of about 20 nm or less.
摘要翻译：在集成电路制造期间，在部分制造的集成电路上印刷具有特殊小特征的图案。使用探针阵列打印图案，每个探针具有：1）在其尖端处的光催化纳米点; 和2）单独控制的光源。部分制造的集成电路的表面包括光化学活性物质。当纳米点被光照射时，活性物质与纳米点接触时发生化学变化。为了打印图案，每个探针光栅扫描其部分制造的集成电路的表面上的相关联的纳米点。当纳米点达到所需位置时，纳米点由光源照射，催化反应物种的变化，从而在该位置进行印刷。随后，选择性地除去反应或未反应的物质，从而在部分制造的集成电路上形成掩模图案。图案中的特征的最小尺寸由纳米点的尺寸确定，并且可以非常小，例如具有约20nm或更小的临界尺寸。

70. 发明授权

US07576441B2 Boron-doped amorphous carbon film for use as a hard etch mask during the formation of a semiconductor device 失效
标题翻译：在半导体器件形成期间用作硬蚀刻掩模的硼掺杂非晶碳膜
公开(公告)号：US07576441B2
公开(公告)日：2009-08-18
申请号：US11214367
申请日：2005-08-29
申请人： Zhiping Yin , Gurtej S. Sandhu
发明人： Zhiping Yin , Gurtej S. Sandhu
IPC分类号： H01L23/544
CPC分类号： H01L21/02115 , H01L21/02274 , H01L21/0332 , H01L21/28088 , H01L21/28123 , H01L21/31133 , H01L21/31144 , H01L21/312 , H01L21/32139 , H01L21/76802 , H01L27/10817 , H01L27/10852 , H01L28/84 , H01L28/90
摘要： A hard mask comprising boron-doped amorphous carbon, and a method for forming the hard mask, provides improved resistance to etches of a variety of materials compared with previous amorphous carbon hard mask layers.
摘要翻译：包含硼掺杂的无定形碳的硬掩模和形成硬掩模的方法与先前的无定形碳硬掩模层相比提供了改进的各种材料的蚀刻耐蚀性。

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