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61. 发明授权

US07148533B2 Memory resistance film with controlled oxygen content 有权
公开(公告)号：US07148533B2
公开(公告)日：2006-12-12
申请号：US11226998
申请日：2005-09-14
申请人： Sheng Teng Hsu , Fengyan Zhang
发明人： Sheng Teng Hsu , Fengyan Zhang
IPC分类号： H01L27/96
CPC分类号： G11C13/0007 , G11C2213/31 , H01L27/016 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641
摘要： A memory cell and method for controlling the resistance properties in a memory material are provided. The method comprises: forming manganite; annealing the manganite in an oxygen atmosphere; controlling the oxygen content in the manganite in response to the annealing; and, controlling resistance through the manganite in response to the oxygen content. The manganite is perovskite-type manganese oxides with the general formula RE1-xAExMnOy, where RE is a rare earth ion and AE is an alkaline-earth ion, with x in the range between 0.1 and 0.5. Controlling the oxygen content in the manganite includes forming an oxygen-rich RE1-xAExMnOy region where y is greater than 3. A low resistance results in the oxygen-rich manganite region. When y is less than 3, a high resistance is formed. More specifically, the process forms a low resistance oxygen-rich manganite region adjacent an oxygen-deficient high resistance manganite region.

62. 发明授权

US06949435B2 Asymmetric-area memory cell 有权
标题翻译：非对称区记忆单元
公开(公告)号：US06949435B2
公开(公告)日：2005-09-27
申请号：US10730726
申请日：2003-12-08
申请人： Sheng Teng Hsu , Fengyan Zhang
发明人： Sheng Teng Hsu , Fengyan Zhang
IPC分类号： H01L21/28 , G11C11/15 , G11C13/00 , H01L21/3205 , H01L21/8239 , H01L21/8246 , H01L23/52 , H01L27/105 , H01L27/115 , H01L27/22 , H01L27/24 , H01L29/68 , H01L43/08 , H01L45/00 , H01L21/336
CPC分类号： H01L27/105 , G11C13/0007 , G11C2213/31 , G11C2213/52 , H01L27/1052 , H01L27/112 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： An asymmetric-area memory cell, and a fabrication method for forming an asymmetric-area memory cell, are provided. The method includes: forming a bottom electrode having an area; forming a CMR memory film overlying the bottom electrode, having an asymmetric area; and, forming a top electrode having an area, less than the bottom electrode area, overlying the CMR film. In one aspect, the CMR film has a first area adjacent the top electrode and a second area, greater than the first area, adjacent the bottom electrode. Typically, the CMR film first area is approximately equal to the top electrode area, although the CMR film second area may be less than the bottom electrode area.
摘要翻译：提供了一种不对称区域存储单元和用于形成非对称区域存储单元的制造方法。该方法包括：形成具有面积的底部电极; 形成覆盖在底部电极上的具有不对称区域的CMR存储膜; 并且形成覆盖CMR膜的具有小于底部电极区域的面积的顶部电极。在一个方面，CMR膜具有邻近顶部电极的第一区域和与底部电极相邻的大于第一区域的第二区域。通常，尽管CMR膜的第二区域可能小于底部电极区域，但是CMR膜的第一区域大致等于顶部电极区域。

63. 发明授权

US06762063B2 Method of fabricating non-volatile ferroelectric transistors 有权
标题翻译：制造非易失性铁电晶体管的方法
公开(公告)号：US06762063B2
公开(公告)日：2004-07-13
申请号：US10395368
申请日：2003-03-24
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： H01L2100
CPC分类号： H01L29/6684 , H01L21/28291 , H01L29/78391
摘要： A method of fabricating a non-volatile ferroelectric memory transistor includes forming a bottom electrode; depositing a ferroelectric layer over an active region beyond the margins of the bottom electrode; depositing a top electrode on the ferroelectric layer; and metallizing the structure to form a source electrode, a gate electrode and a drain electrode. A non-volatile ferroelectric memory transistor includes a bottom electrode formed above a gate region, wherein the bottom electrode has a predetermined area within a peripheral boundary; a ferroelectric layer extending over and beyond the bottom electrode peripheral boundary; and a top electrode formed on said ferroelectric layer.
摘要翻译：制造非挥发性铁电存储晶体管的方法包括：形成底电极; 在超过底部电极的边缘的有源区域上沉积铁电层; 在铁电层上沉积顶部电极; 并且将该结构金属化以形成源电极，栅电极和漏电极。非挥发性铁电存储晶体管包括形成在栅极区域上方的底部电极，其中底部电极在外围边界内具有预定区域; 延伸超过底部电极周边边界的铁电层; 以及形成在所述铁电层上的顶部电极。

64. 发明授权

US06759252B2 Method and device using titanium doped aluminum oxide for passivation of ferroelectric materials 失效
标题翻译：使用钛掺杂氧化铝钝化铁电材料的方法和器件
公开(公告)号：US06759252B2
公开(公告)日：2004-07-06
申请号：US10621850
申请日：2003-07-16
申请人： Fengyan Zhang , Sheng Teng Hsu , Hong Ying
发明人： Fengyan Zhang , Sheng Teng Hsu , Hong Ying
IPC分类号： H01L2102
CPC分类号： H01L28/55 , H01L21/02178 , H01L21/02186 , H01L21/02194 , H01L21/02266 , H01L21/02337 , H01L21/0234 , H01L21/31604 , H01L21/3162 , H01L21/67086 , H01L41/0533
摘要： A passivation layer comprises a titanium-doped aluminum oxide layer for passivation of ferroelectric materials such as Pt/SBt/Ir—Ta—O devices. The titanium-doped aluminum oxide layer for passivation of ferroelectric materials has reduced stress and improved passivation properties, and is easy to deposit and be oxidized. The passivation layer in the MFM Structure resists breakdown and peeling during annealing of the device in a forming gas ambient.
摘要翻译：钝化层包括用于钝化铁电材料例如Pt / SBt / Ir-Ta-O器件的钛掺杂氧化铝层。用于钝化铁电材料的钛掺杂氧化铝层具有减少的应力和改善的钝化性能，并且易于沉积并被氧化。 MFM结构中的钝化层在形成气体环境中抵抗器件退火过程中的击穿和剥离。

65. 发明授权

US06711049B1 One transistor cell FeRAM memory array 失效
标题翻译：一个晶体管单元FeRAM存储器阵列
公开(公告)号：US06711049B1
公开(公告)日：2004-03-23
申请号：US10282985
申请日：2002-10-28
申请人： Sheng Teng Hsu , Jong-Jan Lee , Fengyan Zhang , Nobuyoshi Awaya
发明人： Sheng Teng Hsu , Jong-Jan Lee , Fengyan Zhang , Nobuyoshi Awaya
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A one-transistor FeRAM memory cell array includes an array of ferroelectric transistors arranged in rows and columns, each transistor having a source, a drain, a channel, a gate oxide layer over the channel and a ferroelectric stack formed on the gate oxide layer; word lines connecting the gate ferroelectric stack top electrodes of transistors in a row of the array; a connection to the channel of all transistors in the array formed by a substrate well; a set of first bit lines connecting the sources of all transistors in a column of the array; and a set of second bit lines connecting the drains of all transistors in a column of the array; wherein the ferroelectric stack has opposed edges, which, when projected to a level of the source, drain and channel, are coincident with an abutted edge of the source and the channel and the drain and the channel, respectively.
摘要翻译：单晶体管FeRAM存储单元阵列包括以行和列布置的铁电晶体管阵列，每个晶体管具有源极，漏极，沟道，沟道上的栅极氧化物层和形成在栅极氧化物层上的铁电堆叠; 连接阵列中的晶体管的栅极铁电叠层顶部电极的字线; 连接到由衬底阱形成的阵列中的所有晶体管的沟道; 连接阵列的列中的所有晶体管的源的一组第一位线; 以及连接阵列中的所有晶体管的漏极的一组第二位线; 其中所述铁电堆叠具有相对的边缘，当所述铁电堆叠被投影到所述源极的水平面时，所述漏极和沟道分别与所述源极和所述沟道以及所述漏极和所述沟道的邻接边缘重合。

66. 发明授权

US06673664B2 Method of making a self-aligned ferroelectric memory transistor 失效
标题翻译：制造自对准铁电存储晶体管的方法
公开(公告)号：US06673664B2
公开(公告)日：2004-01-06
申请号：US09978487
申请日：2001-10-16
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang
IPC分类号： H01L218238
CPC分类号： H01L29/51 , H01L21/28291 , H01L21/31691 , H01L27/11502 , H01L27/11507 , H01L29/516
摘要： A method of making a self-aligned ferroelectric memory transistor includes preparing a substrate, shallow trench isolation, n the polysilicon; and forming a gate stack, including: depositing a layer of silicon nitride; selectively etching the silicon nitride, the bottom electrode and the polysilicon; selectively etching the polysilicon to the level of the first dielectric layer; and implanting and activating ions to form a source region and a drain region; forming a sidewall barrier layer; depositing a layer of ferroelectric material; forming a top electrode structure on the ferroelectric material; and finishing the structure, including passivation, oxide depositing and metallization.
摘要翻译：制造自对准铁电存储晶体管的方法包括制备衬底，浅沟槽隔离，n多晶硅; 以及形成栅叠层，包括：沉积氮化硅层; 选择性地蚀刻氮化硅，底部电极和多晶硅; 选择性地将多晶硅蚀刻到第一介电层的水平面; 以及植入和激活离子以形成源区和漏区; 形成侧壁阻挡层; 沉积一层铁电材料; 在铁电材料上形成顶部电极结构; 并完成结构，包括钝化，氧化物沉积和金属化。

67. 发明授权

US06630702B2 Method of using titanium doped aluminum oxide for passivation of ferroelectric materials and devices including the same 有权
公开(公告)号：US06630702B2
公开(公告)日：2003-10-07
申请号：US09819546
申请日：2001-03-27
申请人： Fengyan Zhang , Sheng Teng Hsu , Hong Ying
发明人： Fengyan Zhang , Sheng Teng Hsu , Hong Ying
IPC分类号： H01L27108
CPC分类号： H01L28/55 , H01L21/02178 , H01L21/02186 , H01L21/02194 , H01L21/02266 , H01L21/02337 , H01L21/0234 , H01L21/31604 , H01L21/3162 , H01L21/67086 , H01L41/0533
摘要： A passivation layer comprises a titanium-doped aluminum oxide layer for passivation of ferroelectric materials such as Pt/SBt/Ir—Ta—O devices. The titanium-doped aluminum oxide layer for passivation of ferroelectric materials has reduced stress and improved passivation properties, and is easy to deposit and be oxidized. The passivation layer in the MFM Structure resists breakdown and peeling during annealing of the device in a forming gas ambient.

68. 发明授权

US06616857B2 C-axis oriented lead germanate film 失效
标题翻译： C轴取向锗酸铅膜
公开(公告)号：US06616857B2
公开(公告)日：2003-09-09
申请号：US09942203
申请日：2001-08-29
申请人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01B108
CPC分类号： H01L21/31691 , C23C16/40 , H01L21/31604 , Y10S438/933 , Y10T428/12674 , Y10T428/12701 , Y10T428/12875
摘要： A ferroelectric Pb5Ge3O11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650° C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1×109 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6×10−7 A/cm2 at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb5Ge3O11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.
摘要翻译：铁电Pb5Ge3O11（PGO）薄膜提供金属有机气相沉积（MOCVD）工艺和RTP（快速热处理）退火技术。 PGO膜在450-650℃的温度下基本上以c轴取向结晶.PGO膜的平均粒径为约0.5微米，晶粒尺寸均匀度的偏差小于10％。对于具有Ir电极的150nm厚的膜，获得良好的铁电性能。这些胶片还显示出无疲劳特性：在1x109个开关周期内没有观察到疲劳。泄漏电流随着施加电压的增加而增加，在100kV / cm时为约3.6×10 -7 A / cm 2。介电常数表现出类似于大多数铁电材料的行为，其最大介电常数为约45.这些高质量的MOCVD Pb5Ge3O11膜可用于高密度单晶硅铁氧体存储器应用，因为PGO膜晶粒尺寸的均匀性。

69. 发明授权

US06602720B2 Single transistor ferroelectric transistor structure with high-K insulator and method of fabricating same 失效
标题翻译：具有高K绝缘体的单晶体管铁电晶体管结构及其制造方法
公开(公告)号：US06602720B2
公开(公告)日：2003-08-05
申请号：US09820023
申请日：2001-03-28
申请人： Sheng Teng Hsu , Fengyan Zhang
发明人： Sheng Teng Hsu , Fengyan Zhang
IPC分类号： H01L2100
CPC分类号： H01L29/4983 , H01L21/02189 , H01L21/02197 , H01L21/02271 , H01L21/0228 , H01L21/28291 , H01L21/31053 , H01L21/31604 , H01L21/31691 , H01L29/516 , H01L29/66545 , H01L29/78391
摘要： A ferroelectric transistor gate structure with a ferroelectric gate and a high-k insulator is provided. The high-k insulator may serve as both a gate dielectric and an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing a high-k insulator, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.
摘要翻译：提供了具有铁电栅极和高k绝缘体的铁电晶体管栅极结构。高k绝缘体可以用作栅极电介质和绝缘体，以减少或消除氧或氢扩散到铁电栅极中。还提供了形成铁电栅极结构的方法。该方法包括以下步骤：形成牺牲栅极结构，去除牺牲栅极结构，沉积高k绝缘体，沉积铁电材料，使用CMP抛光铁电材料，以及形成覆盖铁电材料的顶部电极。

70. 发明授权

US06555456B2 Method of forming iridium conductive electrode/barrier structure 失效
公开(公告)号：US06555456B2
公开(公告)日：2003-04-29
申请号：US10037192
申请日：2001-11-09
申请人： Fengyan Zhang , Jer-shen Maa , Sheng Teng Hsu
发明人： Fengyan Zhang , Jer-shen Maa , Sheng Teng Hsu
IPC分类号： H01L213205
CPC分类号： H01L29/456 , H01L21/28291 , H01L28/55 , H01L28/65
摘要： A conductive barrier, useful as a ferroelectric capacitor electrode, having high temperature stability has been provided. This conductive barrier permits the use of iridium (Ir) metal in IC processes involving annealing. Separating silicon substrate from Ir film with an intervening, adjacent, tantalum (Ta) film has been found to very effective in suppressing diffusion between layers. The Ir prevents the interdiffusion of oxygen into the silicon during annealing. A Ta or TaN layer prevents the diffusion of Ir into the silicon. This Ir/TaN structure protects the silicon interface so that adhesion, conductance, hillock, and peeling problems are minimized. The use of Ti overlying the Ir/TaN structure also helps prevent hillock formation during annealing. A method of forming a multilayer Ir conductive structure and Ir ferroelectric electrode are also provided.

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