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61. 发明授权

US07793251B2 Method for increasing the manufacturing yield of programmable logic devices 失效
标题翻译：提高可编程逻辑器件制造产量的方法
公开(公告)号：US07793251B2
公开(公告)日：2010-09-07
申请号：US11275536
申请日：2006-01-12
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G11C17/14 , G11C29/88 , H03K19/17764 , H03K19/17796
摘要： A method for increasing the manufacturing yield of field programmable gate arrays (FPGAS) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.
摘要翻译：一种提高现场可编程门阵列（FPGAS）或其他可编程逻辑器件（PLD）的制造成品率的方法。 FPGA或其他PLD形成在几个部分中，每个部分都有自己的电源总线和输入/输出连接。测试FPGA或其他PLD的每个部分，以识别FPGA或其他PLD中的缺陷。 FPGA或其他PLD根据该部分是否具有可接受的缺陷数量进行排序。为FPGA或其他PLD芯片或部件分配的唯一编号将其识别为部分良好。用于执行和配置FPGA或其他PLD的软件可以使用唯一编号仅对FPGA或其他PLD的已识别功能部分进行编程。结果是产量增加，部分好的FPGA或其他PLD仍然可以被利用。

62. 发明授权

US07765351B2 High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips 失效
标题翻译：用于芯片上多核系统的高带宽低延迟信号量映射协议（SMP）
公开(公告)号：US07765351B2
公开(公告)日：2010-07-27
申请号：US11684687
申请日：2007-03-12
申请人： Pascal A. Nsame , Anthony D. Polson , Nancy H. Pratt , Sebastian T. Ventrone
发明人： Pascal A. Nsame , Anthony D. Polson , Nancy H. Pratt , Sebastian T. Ventrone
IPC分类号： G06F12/00
CPC分类号： G06F9/526 , G06F9/544 , G06F15/167
摘要： A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the network, a memory device communication with the plurality of functional units over the network, and at least one semaphore storage unit communicating with the plurality of functional unites and the memory device over the network. The plurality of functional units include a plurality of functional unit memory locations. The memory device includes a plurality of memory device memory locations. The at least one semaphore storage unit includes a plurality of semaphore storage unit memory locations. The at least one semaphore storage unit controls dynamic movement of the semaphore data among the plurality of functional unit memory locations, the plurality of memory device memory locations, the plurality of semaphore storage unit memory locations, and any combinations therof.
摘要翻译：用于动态管理系统内信号量数据移动的系统和方法。该系统包括但不限于通过网络通信的多个功能单元，与网络上的多个功能单元的存储设备通信，以及与多个功能单元通信的至少一个信号量存储单元，以及存储设备通过网络。多个功能单元包括多个功能单元存储单元。存储器件包括多个存储器件存储器位置。所述至少一个信号量存储单元包括多个信号量存储单元存储单元。所述至少一个信号量存储单元控制所述多个功能单元存储器位置，所述多个存储器设备存储器位置，所述多个信号量存储单元存储器位置中的所述信号量数据的动态移动以及所述多个功能单元存储单元的任何组合。

63. 发明申请

US20090307637A1 METHOD OF DESIGNING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK 有权
标题翻译：设计多状态恢复电路以将状态恢复到功率管理的功能块的方法
公开(公告)号：US20090307637A1
公开(公告)日：2009-12-10
申请号：US12135250
申请日：2008-06-09
申请人： Susan K. Lichtensteiger , Michael R. Ouellette , Raymond W. M. Schuppe , Sebastian T. Ventrone
发明人： Susan K. Lichtensteiger , Michael R. Ouellette , Raymond W. M. Schuppe , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/72
摘要： Methods of designing and testing restore logic for restoring values to storage elements of power-managed logic circuitry. In one implementation, a design method disclosed includes providing a design of the logic circuitry that, when instantiated, will have a number of states it can be returned to upon repowering-up the logic circuitry. Values held by the storage elements are determined and utilized to categorize the storage elements into categories that allow the development of restore logic that will restore the state of the power-managed logic circuitry that is appropriate to the particular powering-up. The restore logic design is tested by modeling it and the power-managed logic circuitry in a hardware description language and simulating the number of states over a number of test cases. If the design and testing are successful, the restore logic can be optimized for instantiation into an actual integrated circuit.
摘要翻译：设计和测试还原逻辑的方法，用于将功能管理逻辑电路的存储元件恢复为值。在一个实施方式中，所公开的设计方法包括提供逻辑电路的设计，当被实例化时，逻辑电路将具有多个状态，可以在重新启动逻辑电路时将其返回。由存储元件保存的值被确定并用于将存储元件分类成允许开发还原逻辑的类别，恢复逻辑将恢复适合于特定供电的功率管理逻辑电路的状态。恢复逻辑设计通过对硬件描述语言进行建模和功耗管理的逻辑电路进行测试，并通过多个测试用例模拟状态数量。如果设计和测试成功，则可以将恢复逻辑优化为实例化为实际的集成电路。

64. 发明申请

US20090239313A1 Integrated Circuit Chip Design Flow Methodology Including Insertion of On-Chip or Scribe Line Wireless Process Monitoring and Feedback Circuitry 有权
标题翻译：集成电路芯片设计流程方法包括插入片上或划线无线过程监控和反馈电路
公开(公告)号：US20090239313A1
公开(公告)日：2009-09-24
申请号：US12343686
申请日：2008-12-24
申请人： Theodoros Anemikos , Ezra D.B. Hall , Sebastian T. Ventrone
发明人： Theodoros Anemikos , Ezra D.B. Hall , Sebastian T. Ventrone
IPC分类号： G06F17/50 , H01L21/66
CPC分类号： G06F17/5045 , G01R31/2884 , G01R31/3025 , G06F2217/12 , H01L2924/0002 , Y02P90/265 , H01L2924/00
摘要： Disclosed are embodiments of a design and manufacturing system and an associated method that allow for design analysis and for insertion, during wafer manufacture, of intra-process monitoring circuitry. These embodiments use a library of pre-qualified intra-process monitoring circuits and a cross-correlation table that links different monitoring circuits with different IC chip components. Specifically, these embodiments analyze integrated circuit chip design data to identify the components designed into the chip. Then, one or more intra-process monitoring circuits are selected from the library and the design data is modified to include the selected monitoring circuit(s).
摘要翻译：公开了设计和制造系统以及相关方法的实施例，其允许在晶片制造期间进行设计分析和插入过程内监控电路。这些实施例使用预定义的内部过程监视电路库和将不同监控电路与不同IC芯片组件链接的互相关表。具体地，这些实施例分析集成电路芯片设计数据以识别设计到芯片中的部件。然后，从库中选择一个或多个进程内监控电路，并且修改设计数据以包括所选择的监视电路。

65. 发明申请

US20090106724A1 Transition Balancing For Noise Reduction/Di/Dt Reduction During Design, Synthesis, and Physical Design 有权
标题翻译：在设计，综合和物理设计过程中减少平衡降噪/减少Di / Dt
公开(公告)号：US20090106724A1
公开(公告)日：2009-04-23
申请号：US11875032
申请日：2007-10-19
申请人： Igor Arsovski , Serafino Bueti , Joseph A. Iadanza , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
发明人： Igor Arsovski , Serafino Bueti , Joseph A. Iadanza , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068
摘要： An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.
摘要翻译：示出了用于降噪的设计结构的实施例，其包括合成顺序锁存器的块，例如流水线电路架构或时钟域，其包括组合逻辑，合成根或主时钟和至少一个相移子域每个块的时钟，将主输入和主输出分配给根时钟，将该块的非主输入和非主输出分配给子域时钟，将根时钟输入分为根时钟输入和相位时钟输入，移位子域时钟输入，为每个块分配不同的相移子域时钟相位偏移，为根时钟和相移子域时钟创建时钟产生电路。

66. 发明申请

US20090051420A1 INTRINSIC RC POWER DISTRIBUTION FOR NOISE FILTERING OF ANALOG SUPPLIES 失效
标题翻译：用于噪声滤波的模拟电源的内部RC功率分配
公开(公告)号：US20090051420A1
公开(公告)日：2009-02-26
申请号：US12196718
申请日：2008-08-22
申请人： Anthony R. Bonaccio , Hayden C. Cranford, JR. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
发明人： Anthony R. Bonaccio , Hayden C. Cranford, JR. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
IPC分类号： H03K5/00
CPC分类号： G05F1/46
摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.
摘要翻译：用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

67. 发明授权

US07489163B2 FPGA powerup to known functional state 失效
标题翻译： FPGA上电到已知的功能状态
公开(公告)号：US07489163B2
公开(公告)日：2009-02-10
申请号：US11869921
申请日：2007-10-10
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Jack R. Smith , Sebastian T. Ventrone , Keith R. Williams
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Jack R. Smith , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/17776 , H03K19/17732 , H03K19/17756 , H03K19/17772
摘要： A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving precious processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronized set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.
摘要翻译：包括非基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）设备。非基于非编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而在上电时节省宝贵的处理时间。公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和冲洗和扫描电路。还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。

68. 发明申请

US20080285338A1 DETERMINING HISTORY STATE OF DATA IN DATA RETAINING DEVICE BASED ON STATE OF PARTIALLY DEPLETED SILICON-ON-INSULATOR 失效
标题翻译：根据部分绝缘硅绝缘体的状态确定数据保留装置中数据的历史状态
公开(公告)号：US20080285338A1
公开(公告)日：2008-11-20
申请号：US12180776
申请日：2008-07-28
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G11C11/34
CPC分类号： G11C11/417
摘要： A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.
摘要翻译：公开了一种用于确定数据保持装置中的数据的历史状态的系统，方法和程序产品。耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）器件的状态被测量以指示PD SOI器件的体电压。 PD SOI器件的体电压可以指示PD SOI器件已经空转多长时间，这间接地指示数据保持器件中的数据未被访问多长时间。因此，本发明可以在数据保留装置的管理中与例如高速缓存替换算法有效地使用。

69. 发明申请

US20080276034A1 Design Structure for Transmitting Data in an Integrated Circuit 审中-公开
标题翻译：集成电路中数据传输的设计结构
公开(公告)号：US20080276034A1
公开(公告)日：2008-11-06
申请号：US12179597
申请日：2008-07-25
申请人： W. Riyon Harding , David W. Milton , Clarence Rosser Ogilvie , Jason E. Rotella , Paul M. Schanely , Sebastian T. Ventrone
发明人： W. Riyon Harding , David W. Milton , Clarence Rosser Ogilvie , Jason E. Rotella , Paul M. Schanely , Sebastian T. Ventrone
IPC分类号： G06F13/00
CPC分类号： G06F17/505
摘要： A design structure, which may be generated by a fabless design company, for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.
摘要翻译：可以由无晶圆厂设计公司生成的用于在驻留在集成电路中的核之间传输数据的设计结构。通过使用位于核心和仲裁器之间的集线器来传输数据。仲裁器维护一个表，其中包含核心之间路由路径的所有有效组合。

70. 发明申请

US20080240222A1 SYSTEM AND METHOD FOR BALANCING DELAY OF SIGNAL COMMUNICATION PATHS THROUGH WELL VOLTAGE ADJUSTMENT 有权
标题翻译：通过良好的电压调整来平衡信号通信的延迟的系统和方法
公开(公告)号：US20080240222A1
公开(公告)日：2008-10-02
申请号：US12136359
申请日：2008-06-10
申请人： Hayden C. Cranford , Joseph A. Iadanza , Sebastian T. Ventrone
发明人： Hayden C. Cranford , Joseph A. Iadanza , Sebastian T. Ventrone
IPC分类号： G01R31/28 , H03K5/159 , H03H7/40 , H03H7/30
CPC分类号： H03K5/133 , H03K2005/00032
摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.
摘要翻译：在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。

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