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1. 发明申请

US20080229265A1 Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees 审中-公开
标题翻译：用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法的设计结构
公开(公告)号：US20080229265A1
公开(公告)日：2008-09-18
申请号：US12129748
申请日：2008-05-30
申请人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F1/10 , G06F17/5045
摘要： Design structure for a clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a design structure for a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.
摘要翻译：公开了用于提供平衡负载的时钟分配网络，结构和方法的设计结构。特别地，用于时钟分配网络的设计结构可以由一个或多个时钟扇出分配电平形成。每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。

2. 发明申请

US20080186051A1 FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH 有权
标题翻译：用于可配置混合逻辑信号分配路径的灵活多模态逻辑单元
公开(公告)号：US20080186051A1
公开(公告)日：2008-08-07
申请号：US11670537
申请日：2007-02-02
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/094
CPC分类号： H03K19/018585 , H03K3/35613 , H03K5/133 , H03K2005/00058 , H03K2005/00208 , H03K2005/00228
摘要： A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译：公开了一种被配置为以多种操作模式之一操作的多模电路。特别地，示例性多模电路可以被配置为以全摆动模式，限制摆动模式，全摆幅至限定摆动转换器模式和限定摆动至全摆幅转换器模式之一进行操作。多模电路的工作模式可以动态地选择。一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。

3. 发明申请

US20080244479A1 STRUCTURE FOR INTRINSIC RC POWER DISTRIBUTION FOR NOISE FILTERING OF ANALOG SUPPLIES 有权
标题翻译：内部RC功率分配结构用于模拟电源的噪声滤波
公开(公告)号：US20080244479A1
公开(公告)日：2008-10-02
申请号：US12053958
申请日：2008-03-24
申请人： Anthony R. BONACCIO , Hayden C. Cranford , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
发明人： Anthony R. BONACCIO , Hayden C. Cranford , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
IPC分类号： G06F17/50
CPC分类号： G05F1/56
摘要： A design structure for intrinsic RC power distribution for noise filtering of analog supplies. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a voltage regulator; a variable resistor coupled to the voltage regulator; and a performance monitor and control circuit providing a feedback loop to the variable resistor.
摘要翻译：用于模拟电源噪声滤波的固有RC功率分配的设计结构。该设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。设计结构包括电压调节器; 耦合到电压调节器的可变电阻器; 以及向可变电阻器提供反馈回路的性能监视和控制电路。

4. 发明申请

US20080240222A1 SYSTEM AND METHOD FOR BALANCING DELAY OF SIGNAL COMMUNICATION PATHS THROUGH WELL VOLTAGE ADJUSTMENT 有权
标题翻译：通过良好的电压调整来平衡信号通信的延迟的系统和方法
公开(公告)号：US20080240222A1
公开(公告)日：2008-10-02
申请号：US12136359
申请日：2008-06-10
申请人： Hayden C. Cranford , Joseph A. Iadanza , Sebastian T. Ventrone
发明人： Hayden C. Cranford , Joseph A. Iadanza , Sebastian T. Ventrone
IPC分类号： G01R31/28 , H03K5/159 , H03H7/40 , H03H7/30
CPC分类号： H03K5/133 , H03K2005/00032
摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.
摘要翻译：在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。

5. 发明申请

US20080148204A1 Clock Distribution Network, Structure, And Method For Providing Balanced Loading In Integrated Circuit Clock Trees 失效
公开(公告)号：US20080148204A1
公开(公告)日：2008-06-19
申请号：US11610963
申请日：2006-12-14
申请人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/62
摘要： A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

6. 发明申请

US20080229266A1 Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees 审中-公开
标题翻译：用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法的设计结构
公开(公告)号：US20080229266A1
公开(公告)日：2008-09-18
申请号：US12129773
申请日：2008-05-30
申请人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/62
摘要： Design structure for a clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.
摘要翻译：公开了用于提供平衡负载的时钟分配网络，结构和方法的设计结构。特别地，时钟分配网络可以由一个或多个时钟扇出分配级别形成。每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。

7. 发明申请

US20080186054A1 DESIGN STRUCTURE FOR A FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH 有权
标题翻译：用于可配置混合逻辑信号分配路径的灵活多模态逻辑单元的设计结构
公开(公告)号：US20080186054A1
公开(公告)日：2008-08-07
申请号：US11848470
申请日：2007-08-31
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/173
CPC分类号： H03K19/018585 , H03K3/35613 , H03K5/133 , H03K2005/00058 , H03K2005/00208 , H03K2005/00228
摘要： A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, a design structure for a exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译：公开了一种被配置为以多种操作模式之一操作的多模电路的设计结构。特别地，用于示例性多模电路的设计结构可以被配置为以全摆动模式，限定摆动模式，全摆幅至限定摆动转换器模式和限定摆动转换模式中的一种运行，摆动转换器模式。多模电路的工作模式可以动态地选择。一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。

8. 发明申请

US20080143416A1 Clock Distribution Network, Structure, And Method For Providing Balanced Loading In Integrated Circuit Clock Trees 失效
标题翻译：用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法
公开(公告)号：US20080143416A1
公开(公告)日：2008-06-19
申请号：US11610848
申请日：2006-12-14
申请人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F1/04 , G06F1/10
CPC分类号： G06F1/10
摘要： A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.
摘要翻译：公开了一种用于提供平衡负载的时钟分配网络，结构和方法。特别地，时钟分配网络可以由一个或多个时钟扇出分配级别形成。每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。

9. 发明申请

US20080218201A1 CML DELAY CELL WITH LINEAR RAIL-TO-RAIL TUNING RANGE AND CONSTANT OUTPUT SWING 失效
公开(公告)号：US20080218201A1
公开(公告)日：2008-09-11
申请号：US12124384
申请日：2008-05-21
申请人： Hayden C. Cranford , Marcel A. Kossel , Thomas E. Morf
发明人： Hayden C. Cranford , Marcel A. Kossel , Thomas E. Morf
IPC分类号： H03K19/003
CPC分类号： H03K5/13 , H03K5/133 , H03K2005/00032 , H03K2005/00208
摘要： A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a current source I0, and a compensation circuit having switching point optimized inverters having a first plurality of transistors having a transconductance βpN and a second plurality of transistors having a transconductance βnN, wherein respective ratios of βnN/βpN determine an inverter switching point of respective switching point optimized inverters, the first and second plurality of transistors having gates coupled to the tuning voltage input of the CML delay cell, wherein the switching point optimized inverters are followed by weighted tail current sources M0N that supply additional currents to the current source I0 at a drain node of the third transistor.

10. 发明申请

US20080126010A1 METHOD AND APPARATUS FOR CONSTRUCTING A SYNCHRONOUS SIGNAL DIAGRAM FROM ASYNCHRONOUSLY SAMPLED DATA 失效
标题翻译：用于构建非同步采样数据同步信号图的方法和装置
公开(公告)号：US20080126010A1
公开(公告)日：2008-05-29
申请号：US11427860
申请日：2006-06-30
申请人： Hayden C. Cranford , Fadi H. Gebara , Jeremy D. Schaub
发明人： Hayden C. Cranford , Fadi H. Gebara , Jeremy D. Schaub
IPC分类号： G06F17/18 , G06F15/00
CPC分类号： H04L1/205 , G01R31/31709
摘要： A method a low cost and production-integrable technique for providing a signal diagram. The data signal is edge-detected and asynchronoulsy sampled (or alternatively a clock signal is latched). The data signal or a second signal is compared to a settable threshold voltage and sampled. The edge and comparison data are folded according to a swept timebase tofind a minimum jitter period. The crossing of the signal diagram edges is determined from a peak of a histogram of the folded edge data. A histogram of ratios of the sample values versus displacement from the position of the crossing location is generated for each threshold voltage. The technique is repeated over a range of settable threshold voltages. Then, the ratio counts are differentiated across the histograms with respect to threshold voltage, from which a signal diagram is populated.
摘要翻译：一种用于提供信号图的低成本和生产可集成技术的方法。数据信号被边缘检测和异步脉冲采样（或者时钟信号被锁存）。将数据信号或第二信号与可设置的阈值电压进行比较并采样。边缘和比较数据根据扫描时基折叠以获得最小抖动周期。信号图边缘的交叉由折叠边缘数据的直方图的峰值确定。对于每个阈值电压产生样本值与交叉位置位置之间的位移比率的直方图。该技术在可设置的阈值电压范围内重复。然后，相对于阈值电压，在直方图之间区分比率计数，从中填充信号图。

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