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61. 发明申请

US20060229641A1 GUIDANCE AND INSERTION SYSTEM 审中-公开
标题翻译：指导和插入系统
公开(公告)号：US20060229641A1
公开(公告)日：2006-10-12
申请号：US11307231
申请日：2006-01-27
申请人： Rajiv Gupta , Steven Barrett , Nevan Hanumara , Jo-Anne Shepard , Alexander Slocum , Conor Walsh
发明人： Rajiv Gupta , Steven Barrett , Nevan Hanumara , Jo-Anne Shepard , Alexander Slocum , Conor Walsh
IPC分类号： A61B19/00
CPC分类号： A61B17/3403 , A61B90/11 , A61B90/39 , A61B2017/00398 , A61B2017/00911 , A61B2017/3407 , A61B2017/3409
摘要： Methods and devices are provided for guiding and inserting a tool into an object, such as tissue. In an exemplary embodiment, a guidance and insertion device is provided that can be remotely controlled to adjust an insertion trajectory of a tool, and to advance the tool into tissue to a desired penetration depth. The tool can be, for example, a biopsy device, a brachytherapy device, or a lumpectomy device. The device can be configured for use with an imaging apparatus, such as computed tomography (CT) images, to allow the device and tool to be operated while viewing the device positioned in relation to a target surgical site. The device can also be configured to be positioned directly on a patient, so as to passively compensate for respiratory chest motion, and it can include features to passively compensate for needle oscillation. In other exemplary embodiments, the device can be entirely disposable.
摘要翻译：提供了用于将工具引导和插入到诸如纸巾的物体中的方法和装置。在示例性实施例中，提供可以被远程控制的引导和插入装置，以调整工具的插入轨迹，并且将工具推进到组织到期望的穿透深度。该工具可以是例如活检装置，近距离放射治疗装置或乳房切除术装置。该装置可被配置为与诸如计算机断层摄影（CT）图像的成像装置一起使用，以允许在查看相对于目标手术部位定位的装置的同时操作装置和工具。该装置还可以被配置为直接定位在患者身上，以便被动地补偿呼吸胸部运动，并且其可以包括被动地补偿针振荡的特征。在其他示例性实施例中，该装置可以是完全一次性的。

62. 发明申请

US20050235991A1 Aerosol generators and methods for producing aerosols 有权
标题翻译：气溶胶发生器和生产气溶胶的方法
公开(公告)号：US20050235991A1
公开(公告)日：2005-10-27
申请号：US11113298
申请日：2005-04-25
申请人： Walter Nichols , Rajiv Gupta , Gene Faison , Kenneth Cox
发明人： Walter Nichols , Rajiv Gupta , Gene Faison , Kenneth Cox
IPC分类号： A61M11/04 , A61M15/00 , A61M16/00 , A62B7/00 , B05B7/16 , B05B9/00 , B05B9/01 , B05B9/08 , B05B17/04 , B65D37/00 , F24J3/00
CPC分类号： A61M15/00 , A61M11/007 , A61M11/042 , A61M15/025 , A61M2016/0021 , B05B7/1686 , B05B9/002 , B05B9/08 , B05B17/04
摘要： An aerosol generator includes a flow passage having an inlet end, an outlet end, and a constriction in the flow passage at the outlet end. A heater is operable to heat liquid in the flow passage to produce a vapor, which is expelled from the outlet end of the flow passage.
摘要翻译：气溶胶发生器包括具有入口端，出口端和在出口端的流动通道中的收缩部的流动通道。加热器可操作以加热流动通道中的液体，以产生从流动通道的出口端排出的蒸气。

63. 发明申请

US20050143866A1 Method and apparatus for generating a volatilized liquid 有权
标题翻译：用于产生挥发性液体的方法和装置
公开(公告)号：US20050143866A1
公开(公告)日：2005-06-30
申请号：US10871536
申请日：2004-06-21
申请人： Douglas McRae , John Felter , Clinton Blake , Mark Capps , Kenneth Cox , David Keeler , Rajiv Gupta
发明人： Douglas McRae , John Felter , Clinton Blake , Mark Capps , Kenneth Cox , David Keeler , Rajiv Gupta
IPC分类号： A61M15/00 , A61M11/00 , A61M11/04 , B05B9/00 , B05B17/00 , G05D23/00
CPC分类号： A61M11/041 , A61M11/007 , A61M11/042 , A61M15/025 , A61M16/0093 , A61M16/1065 , A61M16/202 , A61M2205/3317 , A61M2205/3368 , A61M2209/02 , B05B9/002
摘要： A programmable aerosol generator forms a volatilized liquid by supplying a material in liquid form to a flow passage and heating the flow passage, such that the material volatilizes and expands out of an outlet of the channel. The volatilized material, if desired, mixes with ambient air such that volatilized material condenses to form the aerosol. An apparatus and method for generating such a volatilized liquid, as well as the control and methods of heating, are disclosed as an analytical tool useful for experimental use, a tool useful for production of commercial products or an inhaler device.
摘要翻译：可编程气溶胶发生器通过将液体形式的材料供应到流动通道并加热流路而形成挥发液体，使得材料从通道的出口挥发和膨胀。如果需要，挥发的物质与环境空气混合，使得挥发的物质冷凝形成气溶胶。公开了用于产生这种挥发性液体的装置和方法以及加热控制和方法，作为可用于实验用途的分析工具，可用于生产商业产品或吸入器装置的工具。

64. 发明授权

US06230248B1 Method and apparatus for pre-validating regions in a virtual addressing scheme 失效
标题翻译：用于在虚拟寻址方案中预先验证区域的方法和装置
公开(公告)号：US06230248B1
公开(公告)日：2001-05-08
申请号：US09170140
申请日：1998-10-12
申请人： Stephen G. Burger , James O. Hays , Jonathan K. Ross , William R. Bryg , Rajiv Gupta , Gary N. Hammon , Koichi Yamada
发明人： Stephen G. Burger , James O. Hays , Jonathan K. Ross , William R. Bryg , Rajiv Gupta , Gary N. Hammon , Koichi Yamada
IPC分类号： G06F1216
CPC分类号： G06F12/1036
摘要： A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time. When a virtual-to-physical entry is established for a page in a region having an RID stored in a region register, the RID and VRN are stored in the appropriate fields of the TLB entry. In addition, the valid field is set and the rpV field is set to indicate that the TLB entry contains an active VRN-to-RID mapping, thereby pre-validating the region. When a physical address is translated into a virtual address, a VRN and a VPN are extracted from the virtual address and provided to the TLB. The TLB is searched to find an entry having a set valid field, a set rpV field, and VRN and VPN fields containing entries matching the VRN and VPN extracted from the virtual address. If such an entry is found, the protection and access attributes field is used to determine whether the requested access is allowed. If the requested access is allowed, the PPN from the PPN field of the TLB entry is combined with an offset from the virtual address to produce a physical address that is used to complete the memory access.
摘要翻译：一种方法和装置通过将虚拟区域号（VRN）位和区域标识符（RID）存储在翻译后备缓冲器（TLB）条目中来对虚拟寻址方案中的区域进行预验证。通过将VRN位和RID都存储在TLB表中，可以在执行大多数TLB访问时旁路区域寄存器，从而去除区域寄存器中TLB查找过程的关键路径并提高系统性能。根据本发明的TLB包括具有有效字段，区域预验证有效（rpV）字段，虚拟区域号（VRN）字段，虚拟页号（VPN）字段），区域标识符（RID）字段，保护和访问属性字段以及物理页号（PPN）字段。此外，一组区域寄存器包含在任何给定时间处于活动状态的RID。当在具有存储在区域寄存器中的RID的区域中的页面建立虚拟到物理条目时，RID和VRN被存储在TLB条目的相应字段中。另外，设置有效字段，并且设置rpV字段以指示TLB条目包含活动的VRN到RID映射，从而预先验证该区域。当物理地址被转换为虚拟地址时，从虚拟地址提取VRN和VPN，并提供给TLB。搜索TLB以找到具有设置的有效字段，集合rpV字段的条目，以及包含与从虚拟地址提取的VRN和VPN匹配的条目的VRN和VPN字段。如果找到这样的条目，则使用保护和访问属性字段来确定所请求的访问是否被允许。如果允许所请求的访问，则来自TLB条目的PPN字段的PPN与来自虚拟地址的偏移组合，以产生用于完成存储器访问的物理地址。

65. 发明授权

US5996083A Microprocessor having software controllable power consumption 失效
标题翻译：具有软件可控功耗的微处理器
公开(公告)号：US5996083A
公开(公告)日：1999-11-30
申请号：US514284
申请日：1995-08-11
申请人： Rajiv Gupta , Prasad Raje
发明人： Rajiv Gupta , Prasad Raje
IPC分类号： G06F1/04 , G06F1/08 , G06F1/32 , G06F9/38 , G06F15/78 , G06F1/00
CPC分类号： G06F9/3885 , G06F1/3203 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F1/3296 , G06F9/30083 , G06F9/3836 , G06F9/3869 , Y02B60/1217 , Y02B60/1228 , Y02B60/1282 , Y02B60/1285
摘要： A microprocessor is provided which includes a power control register for controlling the rate of execution and therefore the power consumption of individual functional units. The power control register includes a plurality of fields corresponding to the functional units for storing values that control the power consumption of each. The power control register fields can be set by software which has the much greater ability to look out into the future to determine whether the functional units will be required. The functional units are responsive to the corresponding power control register field to adjust their rate of execution responsive to the value stored therein. The rate of execution can be controlled in a number of different ways: dividing down the clock; removing power to the functional unit; disabling the sensor and/or buffer driver of one or more of the ports in a multi-ported RAM; removing data from the functional unit; and changing the data bus width responsive to the control register field. The microprocessor also includes a latency control register which assures that the functional unit is operational after the functional unit is placed from a low power state to a more fully operational state by changing the corresponding field in the power control register.
摘要翻译：提供了一种微处理器，其包括用于控制执行速率并因此控制各个功能单元的功率消耗的功率控制寄存器。功率控制寄存器包括对应于功能单元的多个场，用于存储控制每个功率消耗的值。功率控制寄存器字段可以通过软件来设置，该软件具有更大的能力，以期望将来确定是否需要功能单元。功能单元响应于相应的功率控制寄存器字段来响应于存储在其中的值来调整其执行速率。执行速度可以通过多种不同的方式进行控制：按时间排序; 去除功能单元的电力; 禁用多端口RAM中的一个或多个端口的传感器和/或缓冲器驱动器; 从功能单元移除数据; 并且响应于控制寄存器字段来改变数据总线宽度。微处理器还包括等待时间控制寄存器，其通过改变功率控制寄存器中的相应字段来确保功能单元在功能单元从低功率状态放置到更完全操作状态之后是可操作的。

66. 发明授权

US5915117A Computer architecture for the deferral of exceptions on speculative instructions 失效
标题翻译：计算机架构，用于推测投机说明上的例外
公开(公告)号：US5915117A
公开(公告)日：1999-06-22
申请号：US949295
申请日：1997-10-13
申请人： Jonathan K. Ross , Jack D. Mills , James O. Hays , Stephen G. Burger , Dale C. Morris , Carol L. Thompson , Rajiv Gupta , Stefan M. Freudenberger , Gary N. Hammond , Ralph M. Kling
发明人： Jonathan K. Ross , Jack D. Mills , James O. Hays , Stephen G. Burger , Dale C. Morris , Carol L. Thompson , Rajiv Gupta , Stefan M. Freudenberger , Gary N. Hammond , Ralph M. Kling
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/3842
摘要： The inventive system and method allows for software control of hardware drral of exceptions in speculative operations, and comprises three components. The first component is processor stored information which reflects the code generation strategy of applications and is used by hardware and the operating system to control exception deferral. The second component is processor stored information set by the operating system to specify to hardware which type of faults should be automatically deferred. The third component is further processor stored information which indicates to the hardware to defer certain exception causing aspects of the speculative operation, while performing other non excepting aspects of the speculative operation. The stored information is set after the operating system exception handler has unsuccessfully attempted fault resolution.
摘要翻译：本发明的系统和方法允许软件控制在推测操作中硬件推迟异常，并且包括三个组件。第一个组件是反映应用程序的代码生成策略的处理器存储信息，由硬件和操作系统用来控制异常延期。第二个组件是由操作系统设置的处理器存储信息，用于指定硬件哪种类型的故障应该自动延迟。第三组件是进一步处理器存储的信息，其指示硬件推迟导致投机操作方面的某些异常，同时执行投机操作的其他非例外方面。存储的信息在操作系统异常处理程序未成功尝试故障解决之后进行设置。

67. 发明授权

US5742804A Instruction prefetch mechanism utilizing a branch predict instruction 失效
标题翻译：使用分支预测指令的指令预取机制
公开(公告)号：US5742804A
公开(公告)日：1998-04-21
申请号：US685607
申请日：1996-07-24
申请人： Tse-Yu Yeh , Mircea Poplingher , Kent G. Fielden , Hans Mulder , Rajiv Gupta , Dale Morris , Michael Schlansker
发明人： Tse-Yu Yeh , Mircea Poplingher , Kent G. Fielden , Hans Mulder , Rajiv Gupta , Dale Morris , Michael Schlansker
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3836 , G06F9/3846
摘要： A processor and method that reduces instruction fetch penalty in the execution of a program sequence of instructions comprises a branch predict instruction that is inserted into the program at a location which precedes the branch. The branch predict instruction has an opcode that specifies a branch as likely to be taken or not taken, and which also specifies a target address of the branch. A block of target instructions, starting at the target address, is prefetched into the instruction cache of the processor so that the instructions are available for execution prior to the point in the program where the branch is encountered. Also specified by the opcode is an indication of the size of the block of target instructions, and a trace vector of a path in the program sequence that leads to the target from the branch predict instruction for better utilization of limited memory bandwidth.
摘要翻译：在程序指令序列的执行中减少指令提取损失的处理器和方法包括在分支之前的位置处插入到程序中的分支预测指令。分支预测指令具有指定可能被采用或未被采用的分支的操作码，并且还指定分支的目标地址。从目标地址开始的目标指令块被预取到处理器的指令高速缓存中，使得指令在程序中遇到分支的点之前可用于执行。操作码还指定了目标指令块的大小的指示，以及由分支预测指令导致目标的程序序列中的路径的跟踪向量，以更好地利用有限的存储器带宽。

68. 发明授权

US5564031A Dynamic allocation of registers to procedures in a digital computer 失效
标题翻译：动态分配寄存器到数字计算机中的程序
公开(公告)号：US5564031A
公开(公告)日：1996-10-08
申请号：US629041
申请日：1996-04-12
申请人： Frederic C. Amerson , Robert M. English , Rajiv Gupta , Tan Watanabe
发明人： Frederic C. Amerson , Robert M. English , Rajiv Gupta , Tan Watanabe
IPC分类号： G06F9/42 , G06F7/72 , G06F9/30 , G06F9/46 , G06F9/48 , G06F12/06
CPC分类号： G06F9/462 , G06F7/72 , G06F9/30123 , G06F9/30134
摘要： In a digital computer, a circular queue of registers in a register file are allocated as temporary local storage for procedures rather than using the known caller/callee save convention in order to minimize main memory references. A called procedure dynamically allocates local registers as needed without regard to registers used by the caller of the procedure or by any callee of the procedure, whereby register allocation is not restricted by any predetermined window size. Local registers, including parameter passing registers, are allocated in the called procedure, rather than a priori at compile time, by adjusting register stack pointer values. Only the number of registers actually required by the procedure need by allocated. Optionally, rotating registers may be allocated among the local registers. Stack pointer values are stored in one of the parameter passing registers when a procedure is called. Hardware register file access circuitry maps virtual register numbers used by the procedures into the hardware register file. Upon return from a procedure, registers are deallocated by adjusting the register stack pointers to the values stored when the procedure was called.
摘要翻译：在数字计算机中，寄存器文件中的寄存器的循环队列被分配为用于过程的临时本地存储器，而不是使用已知的调用者/被调用者保存约定来最小化主存储器引用。被调用的过程根据需要动态地分配本地寄存器，而不考虑由过程的调用者使用的寄存器或过程的任何被调用者，由此寄存器分配不受任何预定窗口大小的限制。本地寄存器（包括参数传递寄存器）在调用过程中被分配，而不是在编译时通过调整寄存器堆栈指针值来先验地分配。只有实际需要的寄存器数量需要分配。可选地，可以在本地寄存器之间分配旋转寄存器。调用过程时，堆栈指针值存储在参数传递寄存器之一中。硬件寄存器文件访问电路将程序使用的虚拟寄存器编号映射到硬件寄存器文件中。从过程返回时，通过将寄存器堆栈指针调整到调用过程时存储的值来释放寄存器。

69. 发明授权

US5514951A Supply-discriminating supply-adaptive electronic system 失效
标题翻译：供应歧视供应自适应电子系统
公开(公告)号：US5514951A
公开(公告)日：1996-05-07
申请号：US226198
申请日：1994-04-11
申请人： Raouf Halim , Rajiv Gupta , Daryush Shamlou
发明人： Raouf Halim , Rajiv Gupta , Daryush Shamlou
IPC分类号： G06F1/26 , G05F1/56 , G05F3/30 , H02M3/07 , G05F1/40
CPC分类号： H02M3/07 , Y10S323/901
摘要： A novel supply discriminator circuit is disclosed for detecting the level of a supply voltage during power-up of a system for configuring an integrated analog circuit such as a PCMCIA card. The circuit compares a reference voltage with a divided down supply voltage and latches the result a predetermined delay later. The delay thus provides timing for the supply voltage to stabilize after power-up to assure accurate detection, as well as noise immunity from other devices.
摘要翻译：公开了一种新颖的电源鉴别器电路，用于在用于配置诸如PCMCIA卡的集成模拟电路的系统的上电期间检测电源电压的电平。该电路将参考电压与分压电源电压进行比较，并将结果锁存在预定延迟之后。延迟因此提供供电电压的定时，以在上电后稳定，以确保准确的检测以及来自其他设备的抗噪声能力。

70. 发明授权

US5404484A Cache system for reducing memory latency times 失效
标题翻译：缓存系统，用于减少内存延迟时间
公开(公告)号：US5404484A
公开(公告)日：1995-04-04
申请号：US945561
申请日：1992-09-16
申请人： Michael S. Schlansker , Vinod K. Kathail , Rajiv Gupta
发明人： Michael S. Schlansker , Vinod K. Kathail , Rajiv Gupta
IPC分类号： G06F9/38 , G06F12/08 , G06F12/12
CPC分类号： G06F9/30047 , G06F12/0862 , G06F12/0888 , G06F9/383 , G06F2212/6022 , G06F2212/6028
摘要： The improved cache system reduces the effects of latency times by utilizing a preload instruction inserted by the compiler into the code. The preload instruction is sent sufficiently in advance of the corresponding load instruction to guarantee that the relevant data is in the cache memory when the load instruction is received. In addition, the invention prevents the pollution of the cache with data that will only be used once during the expected lifetime of the data in the cache. This second feature of the invention assures that a large number of references to data that will only be used once does not result in the contents of the cache being replaced with the subsequent need to reload the contents after the data references have been completed.
摘要翻译：改进的缓存系统通过利用编译器插入到代码中的预加载指令来减少延迟时间的影响。预加载指令在相应的加载指令之前被充分发送，以便在接收到加载指令时保证相关数据在高速缓冲存储器中。此外，本发明通过在高速缓存中的数据的期望寿命期间仅使用一次的数据来防止高速缓存的污染。本发明的第二个特征确保了大量仅仅使用一次的数据的引用不会导致高速缓存的内容被替换为在数据引用完成之后随后需要重新加载内容。

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