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    • 1. 发明授权
    • Microprocessor having software controllable power consumption
    • 具有软件可控功耗的微处理器
    • US5996083A
    • 1999-11-30
    • US514284
    • 1995-08-11
    • Rajiv GuptaPrasad Raje
    • Rajiv GuptaPrasad Raje
    • G06F1/04G06F1/08G06F1/32G06F9/38G06F15/78G06F1/00
    • G06F9/3885G06F1/3203G06F1/324G06F1/3275G06F1/3287G06F1/3296G06F9/30083G06F9/3836G06F9/3869Y02B60/1217Y02B60/1228Y02B60/1282Y02B60/1285
    • A microprocessor is provided which includes a power control register for controlling the rate of execution and therefore the power consumption of individual functional units. The power control register includes a plurality of fields corresponding to the functional units for storing values that control the power consumption of each. The power control register fields can be set by software which has the much greater ability to look out into the future to determine whether the functional units will be required. The functional units are responsive to the corresponding power control register field to adjust their rate of execution responsive to the value stored therein. The rate of execution can be controlled in a number of different ways: dividing down the clock; removing power to the functional unit; disabling the sensor and/or buffer driver of one or more of the ports in a multi-ported RAM; removing data from the functional unit; and changing the data bus width responsive to the control register field. The microprocessor also includes a latency control register which assures that the functional unit is operational after the functional unit is placed from a low power state to a more fully operational state by changing the corresponding field in the power control register.
    • 提供了一种微处理器,其包括用于控制执行速率并因此控制各个功能单元的功率消耗的功率控制寄存器。 功率控制寄存器包括对应于功能单元的多个场,用于存储控制每个功率消耗的值。 功率控制寄存器字段可以通过软件来设置,该软件具有更大的能力,以期望将来确定是否需要功能单元。 功能单元响应于相应的功率控制寄存器字段来响应于存储在其中的值来调整其执行速率。 执行速度可以通过多种不同的方式进行控制:按时间排序; 去除功能单元的电力; 禁用多端口RAM中的一个或多个端口的传感器和/或缓冲器驱动器; 从功能单元移除数据; 并且响应于控制寄存器字段来改变数据总线宽度。 微处理器还包括等待时间控制寄存器,其通过改变功率控制寄存器中的相应字段来确保功能单元在功能单元从低功率状态放置到更完全操作状态之后是可操作的。
    • 4. 发明授权
    • Cover instruction and asynchronous backing store switch
    • 封面指令和异步后备存储开关
    • US6065114A
    • 2000-05-16
    • US64091
    • 1998-04-21
    • Achmed Rumi ZahirJonathan K. RossCarol ThompsonCary CoutantPrasad RajeSunil Saxena
    • Achmed Rumi ZahirJonathan K. RossCarol ThompsonCary CoutantPrasad RajeSunil Saxena
    • G06F9/30G06F9/40G06F9/46G06F9/48
    • G06F9/4812G06F9/3009G06F9/30127G06F9/30134G06F9/4425G06F9/461
    • A computer-implemented method of switching contexts in a processor is provided. The processor includes a register stack (RS) that has first and second portions. The processor includes a register stack engine (RSE) to exchange information, in one of instruction execution dependent and independent modes between the second portion and the storage area. The computer implemented method of switching contexts includes the following steps: It is determined whether an interrupt occurred; a first register (IFM) configured to store a content of a second register (CFM) is invalidated, the CFM is configured to store control information related to the first portion; it is determined whether an interrupt handler needs to access the RS; and if so, the IFM is validated, the content of the CFM is copied to the IFM, and RSE is caused to exchange information between both the first and second portions of the RS and the storage area. On return from interruption, if IFM is validated, CFM is restored from IFM else CFM remains unchanged. The COVER instruction enables lightweight interrupt handling in a processor with a Register Stack.
    • 提供了一种在处理器中切换上下文的计算机实现的方法。 处理器包括具有第一和第二部分的寄存器堆栈(RS)。 该处理器包括一个寄存器堆栈引擎(RSE),用于在第二部分和存储区域之间以指令执行相关和独立模式之一交换信息。 计算机实现的切换上下文的方法包括以下步骤:确定是否发生中断; 配置为存储第二寄存器(CFM)的内容的第一寄存器(IFM)无效,所述CFM被配置为存储与所述第一部分相关的控制信息; 确定中断处理程序是否需要访问RS; 如果是,则IFM被验证,CFM的内容被复制到IFM,并且使RSE在RS的第一和第二部分与存储区域之间交换信息。 从中断返回时,如果IFM被验证,则从IFM恢复CFM,否则CFM保持不变。 COVER指令在具有寄存器堆栈的处理器中实现轻量级中断处理。
    • 5. 发明授权
    • Method for storing and decoding instructions for a microprocessor having
a plurality of function units
    • 用于存储和解码具有多个功能单元的微处理器的指令的方法
    • US5930508A
    • 1999-07-27
    • US871128
    • 1997-06-09
    • Paolo FaraboschiPrasad Raje
    • Paolo FaraboschiPrasad Raje
    • G06F9/30G06F9/318G06F9/38G06F7/00
    • G06F9/3808G06F9/30152G06F9/30178G06F9/3816G06F9/3822G06F9/3885
    • A method and apparatus for compacting VLIW instructions in a processor having multiple functional units and including a buffer for storing compacted instructions, wherein NOP codes are eliminated from the compacted instruction and each compacted instruction includes words which contain an operation code directing the operation of one of the functional units, a dispersal code, and a delimiter code, wherein an alignment circuit parses each compacted instruction from the buffer based upon the delimiter codes of the words and aligns the compacted instruction in an alignment buffer and a dispersal circuit transfers each word of the compacted instruction stored in the alignment buffer into at least one operational field of a dispersed instruction buffer which stores an executable instruction having an operational field corresponding to each one of the functional units. Another embodiment is also shown which interleaves the bits of a buffer, alignment circuit, alignment buffer, dispersal circuit and dispersed instruction buffer to reduce the circuit area required for expanding the compacted instruction.
    • 一种用于在具有多个功能单元的处理器中压缩VLIW指令的方法和装置,并且包括用于存储压缩指令的缓冲器,其中从压缩指令中消除NOP代码,并且每个压缩指令包括字,其包含指示操作代码 功能单元,分散代码和分隔符代码,其中对齐电路基于单词的定界符代码对缓冲器中的每个压缩指令进行解析,并将对准缓冲器中的压缩指令对准,并且扩散电路将每个单词 存储在对准缓冲器中的压缩指令到分散指令缓冲器的至少一个操作区域中,该分散指令缓冲器存储具有与每个功能单元相对应的操作区域的可执行指令。 还示出了另一个实施例,其交替缓冲器,对准电路,对准缓冲器,分散电路和分散指令缓冲器的位,以减少扩展压缩指令所需的电路面积。