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1. 发明授权

US5915117A Computer architecture for the deferral of exceptions on speculative instructions 失效
标题翻译：计算机架构，用于推测投机说明上的例外
公开(公告)号：US5915117A
公开(公告)日：1999-06-22
申请号：US949295
申请日：1997-10-13
申请人： Jonathan K. Ross , Jack D. Mills , James O. Hays , Stephen G. Burger , Dale C. Morris , Carol L. Thompson , Rajiv Gupta , Stefan M. Freudenberger , Gary N. Hammond , Ralph M. Kling
发明人： Jonathan K. Ross , Jack D. Mills , James O. Hays , Stephen G. Burger , Dale C. Morris , Carol L. Thompson , Rajiv Gupta , Stefan M. Freudenberger , Gary N. Hammond , Ralph M. Kling
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/3842
摘要： The inventive system and method allows for software control of hardware drral of exceptions in speculative operations, and comprises three components. The first component is processor stored information which reflects the code generation strategy of applications and is used by hardware and the operating system to control exception deferral. The second component is processor stored information set by the operating system to specify to hardware which type of faults should be automatically deferred. The third component is further processor stored information which indicates to the hardware to defer certain exception causing aspects of the speculative operation, while performing other non excepting aspects of the speculative operation. The stored information is set after the operating system exception handler has unsuccessfully attempted fault resolution.
摘要翻译：本发明的系统和方法允许软件控制在推测操作中硬件推迟异常，并且包括三个组件。第一个组件是反映应用程序的代码生成策略的处理器存储信息，由硬件和操作系统用来控制异常延期。第二个组件是由操作系统设置的处理器存储信息，用于指定硬件哪种类型的故障应该自动延迟。第三组件是进一步处理器存储的信息，其指示硬件推迟导致投机操作方面的某些异常，同时执行投机操作的其他非例外方面。存储的信息在操作系统异常处理程序未成功尝试故障解决之后进行设置。

2. 发明授权

US5859999A System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers 失效
标题翻译：用于通过具有对应于多个寄存器的至少一个位的掩码恢复谓词寄存器的系统
公开(公告)号：US5859999A
公开(公告)日：1999-01-12
申请号：US725573
申请日：1996-10-03
申请人： Dale C. Morris , Jack D. Mills
发明人： Dale C. Morris , Jack D. Mills
IPC分类号： G06F9/32 , G06F9/305 , G06F9/34 , G06F9/38 , G06F9/42 , G06F9/312
CPC分类号： G06F9/3842 , G06F9/30072
摘要： The present invention provides a method and apparatus for restoring a predicate register set. One embodiment of the invention includes decoding a first instruction which specifies a restoring operation to be performed on a predicate register set. In response to the first instruction, a mask is used to select a plurality of the predicate registers that are to be restored. The mask of the present invention consists of a first set of bits, with each bit of the first set of bits corresponding to a register in the predicate register set. When a bit of the first set of bits is set to one, the predicate register corresponding to that bit is restored. In one embodiment, the mask further includes one bit corresponding to a plurality of registers in the predicate register set, wherein when that bit is set to one, the plurality of registers corresponding to that bit are restored.
摘要翻译：本发明提供一种用于恢复谓词寄存器组的方法和装置。本发明的一个实施例包括对指定要在谓词寄存器集上执行的恢复操作的第一指令进行解码。响应于第一条指令，使用掩码来选择要恢复的多个谓词寄存器。本发明的掩模由第一组位组成，其中第一组位的每个位对应于谓词寄存器组中的寄存器。当第一组位的位被设置为1时，对应于该位的谓词寄存器被恢复。在一个实施例中，掩码还包括对应于谓词寄存器集合中的多个寄存器的一个位，其中当该位被设置为1时，与该位相对应的多个寄存器被恢复。

3. 发明授权

US5442756A Branch prediction and resolution apparatus for a superscalar computer processor 失效
标题翻译：用于超标量计算机处理器的分支预测和分辨率装置
公开(公告)号：US5442756A
公开(公告)日：1995-08-15
申请号：US922855
申请日：1992-07-31
申请人： Edward T. Grochowski , Donald B. Alpert , Jack D. Mills , Uri C. Weiser
发明人： Edward T. Grochowski , Donald B. Alpert , Jack D. Mills , Uri C. Weiser
IPC分类号： G06F9/318 , G06F9/38
CPC分类号： G06F9/30192 , G06F9/3806 , G06F9/3812 , G06F9/3836 , G06F9/3844 , G06F9/3857 , G06F9/3861 , G06F9/3867
摘要： An apparatus and method for improving the performance of superscalar pipelined computers using branch prediction and verification that the predicted branch is correct. A predicted branch may be resolved in one of two distinct pipeline stages, and a method is provided for handling branches that are resolved in either of the pipeline stages. A branch verification method is provided that verifies that the architecturally correct instructions are in the decode and execution stages. Furthermore, two sets of prefetch buffers are provided to allow branch prediction when multiple clock decoding is required by a multi-clock instruction.
摘要翻译：一种使用预测分支正确的分支预测和验证来提高超标量流水线计算机性能的装置和方法。预测分支可以在两个不同流水线阶段之一中解决，并且提供了一种用于处理在任一流水线阶段中解决的分支的方法。提供一种分支验证方法，其验证架构上正确的指令处于解码和执行阶段。此外，当多时钟指令需要多个时钟解码时，提供两组预取缓冲器以允许分支预测。

4. 发明授权

US5991874A Conditional move using a compare instruction generating a condition field 失效
标题翻译：使用生成条件字段的比较指令进行条件移动
公开(公告)号：US5991874A
公开(公告)日：1999-11-23
申请号：US660094
申请日：1996-06-06
申请人： Jack D. Mills , Donald Alpert
发明人： Jack D. Mills , Donald Alpert
IPC分类号： G06F9/30 , G06F9/315 , G06F9/38 , G06F7/00 , G06F7/38
CPC分类号： G06F9/30032 , G06F9/30021 , G06F9/30036 , G06F9/30072 , G06F9/384
摘要： An apparatus for use in a computer system comprises a first storage area and a circuit, coupled to the first storage area, configured to perform a comparison of a data element A with a data element B. In response to a single instruction, the circuit performs the comparison and outputs a condition field of at least one bits when the comparison of A and B is TRUE, or else the circuit outputs the ones-complement of the condition field when the comparison of A and B is FALSE. The circuit may be used in conjunction with a sequence of instructions to select bits from a first data element and bits from a second data element using the one or more condition field bits.
摘要翻译：一种在计算机系统中使用的装置包括耦合到第一存储区域的第一存储区域和电路，被配置为执行数据元素A与数据元素B的比较。响应于单个指令，电路执行当A和B的比较为TRUE时，比较并输出至少一个比特的条件字段，否则当A和B的比较为FALSE时，电路输出条件字段的补码。电路可以与指令序列一起使用，以使用一个或多个条件字段位来从第一数据元素选择位和来自第二数据元素的位。

5. 发明授权

US5948095A Method and apparatus for prefetching data in a computer system 失效
公开(公告)号：US5948095A
公开(公告)日：1999-09-07
申请号：US1548
申请日：1997-12-31
申请人： Judge K. Arora , Jack D. Mills , Jerome C. Huck
发明人： Judge K. Arora , Jack D. Mills , Jerome C. Huck
IPC分类号： G06F9/38
CPC分类号： G06F9/3861 , G06F9/383
摘要： A method and apparatus for prefetching data in a computer system that includes a processor. A prefetch instruction is executed and, in response, data is prefetched from a memory location. It is determined if a memory exception occurred during the prefetching of the data. If a memory exception occurred, the exception is handled if the prefetch instruction indicates to do so.

6. 发明授权

US5606676A Branch prediction and resolution apparatus for a superscalar computer processor 失效
标题翻译：用于超标量计算机处理器的分支预测和分辨率装置
公开(公告)号：US5606676A
公开(公告)日：1997-02-25
申请号：US386066
申请日：1995-02-09
申请人： Edward T. Grochowski , Donald B. Alpert , Jack D. Mills , Uri C. Weiser
发明人： Edward T. Grochowski , Donald B. Alpert , Jack D. Mills , Uri C. Weiser
IPC分类号： G06F9/318 , G06F9/38
CPC分类号： G06F9/30192 , G06F9/3806 , G06F9/3812 , G06F9/3836 , G06F9/3844 , G06F9/3857 , G06F9/3861 , G06F9/3867
摘要： An apparatus and method for improving the performance of superscalar pipelined computers using branch prediction and verification that the predicted branch is correct. A predicted branch may be resolved in one of two distinct pipeline stages, and a method is provided for handling branches that are resolved in either of the pipeline stages. A branch verification method is provided that verifies that the architecturally correct instructions are in the decode and execution stages. Furthermore, two sets of prefetch buffers are provided to allow branch prediction when multiple clock decoding is required by a multi-clock instruction.
摘要翻译：一种使用预测分支正确的分支预测和验证来提高超标量流水线计算机性能的装置和方法。预测分支可以在两个不同流水线阶段之一中解决，并且提供了一种用于处理在任一流水线阶段中解决的分支的方法。提供一种分支验证方法，其验证架构上正确的指令处于解码和执行阶段。此外，当多时钟指令需要多个时钟解码时，提供两组预取缓冲器以允许分支预测。

7. 发明授权

US5559986A Interleaved cache for multiple accesses per clock cycle in a microprocessor 失效
标题翻译：在微处理器中每个时钟周期进行多次访问的交错缓存
公开(公告)号：US5559986A
公开(公告)日：1996-09-24
申请号：US191052
申请日：1994-02-02
申请人： Donald B. Alpert , Mustafiz R. Choudhury , Jack D. Mills
发明人： Donald B. Alpert , Mustafiz R. Choudhury , Jack D. Mills
IPC分类号： G06F12/08 , G11C11/401
CPC分类号： G06F12/0851 , G06F12/0857 , G06F12/0859 , G06F2212/1028 , Y02B60/1225
摘要： An interleaved cache is used for multiple data accesses per clock in a microprocessor. The cache includes a storage array having multiple banks of single-ported memory cells for storing data, a bank selector for selecting banks in the storage array simultaneously according to the multiple data accesses, and a datapath for transfering data between execution units in the microprocessor and the storage array. The cache of the present invention also includes contention logic for prioritizing the multiple data accesses when multiple data accesses are to be same bank.
摘要翻译：在微处理器中每个时钟使用交错缓存进行多次数据访问。高速缓存包括具有用于存储数据的多个单端口存储器单元组的存储阵列，用于根据多个数据访问同时选择存储阵列中的存储体的存储体选择器，以及用于在微处理器中的执行单元之间传送数据的数据通路，以及存储阵列。本发明的高速缓存还包括用于在多个数据访问是同一个银行时优先考虑多个数据访问的争用逻辑。

8. 发明授权

US06205544B1 Decomposition of instructions into branch and sequential code sections 有权
标题翻译：将指令分解为分支和顺序代码段
公开(公告)号：US06205544B1
公开(公告)日：2001-03-20
申请号：US09217762
申请日：1998-12-21
申请人： Jack D. Mills , Christopher B. Wilkerson
发明人： Jack D. Mills , Christopher B. Wilkerson
IPC分类号： G06F1500
CPC分类号： G06F9/3889 , G06F9/321 , G06F9/3802 , G06F9/3804 , G06F9/3844 , G06F9/3877
摘要： The decomposition of instructions into separate sequential and branch instruction code sections. In one embodiment, a system including a first store to store a first code section including only branch instructions and a second store to store a second code section including only sequential instructions. In another embodiment, the system also includes a processor having a first engine to process the branch instructions, and a second engine to process the sequential instructions.
摘要翻译：指令分解为单独的顺序和分支指令代码段。在一个实施例中，一种包括第一存储器的系统，用于存储仅包括分支指令的第一代码段和第二存储器，以存储仅包括顺序指令的第二代码段。在另一个实施例中，系统还包括具有处理分支指令的第一引擎的处理器和用于处理顺序指令的第二引擎。

9. 发明授权

US06119218A Method and apparatus for prefetching data in a computer system 有权
标题翻译：用于在计算机系统中预取数据的方法和装置
公开(公告)号：US06119218A
公开(公告)日：2000-09-12
申请号：US349839
申请日：1999-07-08
申请人： Judge K. Arora , Jack D. Mills , Jerome C. Huck
发明人： Judge K. Arora , Jack D. Mills , Jerome C. Huck
IPC分类号： G06F9/38
CPC分类号： G06F9/3861 , G06F9/383
摘要： A method and apparatus for prefetching data in a computer system that inces a processor. A prefetch instruction is executed and, in response, data is prefetched from a memory location. It is determined if a memory exception occurred during the prefetching of the data. If a memory exception occurred, the exception is handled if the prefetch instruction indicates to do so.
摘要翻译：一种用于在包括处理器的计算机系统中预取数据的方法和装置。执行预取指令，作为响应，从存储器位置预取数据。确定在数据预取期间是否发生内存异常。如果发生内存异常，则如果预取指令指示这样做，则会处理异常。

10. 发明授权

US5889984A Floating point and integer condition compatibility for conditional branches and conditional moves 失效
标题翻译：条件分支和条件移动的浮点和整数条件兼容性
公开(公告)号：US5889984A
公开(公告)日：1999-03-30
申请号：US699424
申请日：1996-08-19
申请人： Jack D. Mills
发明人： Jack D. Mills
IPC分类号： G06F9/30 , G06F9/315 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/00
CPC分类号： G06F9/30021 , G06F9/30032 , G06F9/30072 , G06F9/30094
摘要： In a processor where separate integer and floating point units are utilized, conditions generated in the integer unit are transferred and made compatible for use in the floating point unit by floating point conditional branch and move operations. Conversely, conditions generated in the floating point unit are transferred and made compatible for use in the integer unit by integer conditional branch and move operations. By providing semantic compatibility of conditions with conditional operations in both integer and floating point units, conditions can be generated in one numeric unit and operated in the other.
摘要翻译：在使用单独的整数和浮点单位的处理器中，以整数单位产生的条件通过浮点条件分支和移动操作被传送并使其与浮点单元相兼容。相反，在浮点单元中生成的条件通过整数条件分支和移动操作被传送并使其与整数单位相兼容。通过将条件与条件操作的语义兼容性提供在整数和浮点单元中，可以以一个数字单位生成条件并在另一个数字单元中操作。

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