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61. 发明授权

US06389374B1 OBDD variable ordering using sampling based schemes 有权
标题翻译： OBDD变量排序使用基于抽样的方案
公开(公告)号：US06389374B1
公开(公告)日：2002-05-14
申请号：US09187055
申请日：1998-11-05
申请人： Jawahar Jain , Yuan Lu
发明人： Jawahar Jain , Yuan Lu
IPC分类号： G06F1710
CPC分类号： G06F17/504
摘要： A system and method for determining variable orders for decision diagrams. The variable orders are determined by sampling subspaces of a Boolean space representing a function or circuit. The subspaces are formed in a variety of ways, including through the use of abstraction, decomposition, partial assignments, and circuit subspaces.
摘要翻译：用于确定决策图变量顺序的系统和方法。变量顺序通过对表示函数或电路的布尔空间的子空间进行抽样来确定。子空间以各种方式形成，包括通过使用抽象，分解，部分分配和电路子空间。

62. 发明授权

US06267821B1 Substrate clamp design for minimizing substrate to clamp sticking during thermal processing of thermally flowable layers 有权
标题翻译：基板夹具设计，用于最大限度地减少热可流层的热处理过程中的基板以贴紧
公开(公告)号：US06267821B1
公开(公告)日：2001-07-31
申请号：US09332383
申请日：1999-06-14
申请人： Chih-Yuan Lu
发明人： Chih-Yuan Lu
IPC分类号： C23C1600
CPC分类号： H01L21/68721 , C23C16/4401 , C23C16/4585 , H01L21/68735 , H01L21/68757
摘要： A clamp for fixturing a substrate when forming and thermal processing upon the substrate a thermally flowable layer. The clamp is formed from a backing member connected to a top member through a mechanical means. The backing member and the top member are sized such that a substrate may be clamped between the backing member and the top member. A portion of the top member overlaps the substrate and leaves exposed a first portion of the substrate when the substrate is clamped between the backing member and the top member. The top member has a cross-sectional profile such that a thermally flowable layer residue formed upon the top member when a thermally flowable layer is formed upon the substrate will not flow from the top member and bridge to the thermally flowable layer when the thermally flowable layer is thermally processed.
摘要翻译：一种用于在基底上形成热处理并热处理热可流动层时固定基板的夹具。夹具由通过机械装置连接到顶部构件的背衬构件形成。所述背衬构件和所述顶部构件的尺寸设计成使得衬底可被夹持在所述衬垫构件和所述顶部构件之间。顶部构件的一部分与衬底重叠，并且当衬底夹持在衬垫构件和顶部构件之间时，露出衬底的第一部分。顶部构件具有横截面轮廓，使得当热可流动层形成在基底上时形成在顶部构件上的可热流动的层残留物将不会从顶部构件流动并桥接到热可流动层，当热可流动层被热处理。

63. 发明授权

US06262449B1 High density dynamic random access memory cell structure having a polysilicon pillar capacitor 失效
标题翻译：具有多晶硅柱电容器的高密度动态随机存取存储单元结构
公开(公告)号：US06262449B1
公开(公告)日：2001-07-17
申请号：US08709964
申请日：1996-09-09
申请人： Chih-Yuan Lu , Horng-Huei Tseng
发明人： Chih-Yuan Lu , Horng-Huei Tseng
IPC分类号： H01L27108
CPC分类号： H01L27/1085 , H01L27/10805 , H01L28/40
摘要： A method for manufacturing an array of stacked capacitor is described that utilizes the sidewall of the capacitor node contact to increase the capacitance on a dynamic random access memory (DRAM) cell. The area occupied by the stacked capacitor is also restricted to the area over the FET source/drain area, thereby providing for the further reduction of the cell size. The method using a single mask level to form node contact openings in a thick insulating layer over the source/drain areas used for the node contact. A doped polysilicon layer is deposited filling the node contact openings and conformally coating the substrate. The polysilicon layer is oxidized to the thick insulating layer but not in the node contact openings. The oxidized portion of the polysilicon layer and the thick insulating layer are removed concurrently in a wet etch leaving free standing pillar-shaped bottom electrodes that also serve as the node contacts. The array of pillar-shaped stacked capacitors are completed by forming a interelectrode dielectric layer on the bottom electrodes and then depositing and patterning another doped polysilicon to form the top electrodes.
摘要翻译：描述了制造堆叠电容器阵列的方法，其利用电容器节点接触件的侧壁来增加动态随机存取存储器（DRAM）单元上的电容。层叠电容器占据的面积也限于FET源极/漏极区域上的面积，从而进一步减小电池尺寸。使用单个掩模级别的方法在用于节点接触的源极/漏极区域上的厚绝缘层中形成节点接触开口。沉积掺杂的多晶硅层，填充节点接触开口并保形地涂覆衬底。多晶硅层被氧化成厚的绝缘层，但不在节点接触开口中。在湿蚀刻中同时去除多晶硅层的氧化部分和厚的绝缘层，留下也用作节点接触的独立的柱状底部电极。柱状堆叠电容器的阵列通过在底部电极上形成电极间电介质层，然后沉积和构图另一个掺杂多晶硅以形成顶部电极来完成。

64. 发明授权

US06206441B1 Apparatus and method for transferring wafers by robot 有权
标题翻译：机器人传送晶片的装置及方法
公开(公告)号：US06206441B1
公开(公告)日：2001-03-27
申请号：US09366226
申请日：1999-08-03
申请人： Ming-Chien Wen , Chuan-Yuan Lu , Chi-Yun Tseng , Su-Yi Doung
发明人： Ming-Chien Wen , Chuan-Yuan Lu , Chi-Yun Tseng , Su-Yi Doung
IPC分类号： B25J1506
CPC分类号： H01L21/67259 , Y10S294/907 , Y10S414/141
摘要： An apparatus for transferring wafers by a robot blade and a method for using the apparatus are disclosed. In the apparatus, a robot blade that is equipped with distance sensors mounted in a bottom surface of the blade is provided which senses the distance between the bottom surface of the robot blade and an adjacent surface below the robot blade such that any possible scratching of the adjacent surface is eliminated. The adjacent surface below the robot blade may be a wafer surface in a wafer cassette, or a wafer pedestal surface in a process machine. The distance sensors are mounted in recesses in the bottom surface of the blade which may be suitably capacitance sensors, ultrasonic sensors or optical sensors. The distance sensed by the distance sensors is analyzed by a controller and compared to a predetermined value of a minimum allowable distance such that any danger of scratching the adjacent surface is eliminated.
摘要翻译：公开了一种通过机器人刀片传送晶片的装置和使用该装置的方法。在该装置中，设置有安装在叶片的底表面中的距离传感器的机器人叶片，其感测机器人叶片的底表面和机器人叶片下方的相邻表面之间的距离，使得可能划伤相邻表面被消除。机器人刀片下面的相邻表面可以是晶片盒中的晶片表面，或处理机器中的晶片基座表面。距离传感器安装在叶片底面的凹槽中，其可以是适当的电容传感器，超声波传感器或光学传感器。由距离传感器感测的距离由控制器分析，并与最小可允许距离的预定值进行比较，从而消除了刮擦相邻表面的任何危险。

65. 发明授权

US06171923B2 Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor 有权
标题翻译：在包含二维沟槽电容器的SOI晶片上制造DRAM单元结构的方法
公开(公告)号：US06171923B2
公开(公告)日：2001-01-09
申请号：US09379228
申请日：1999-08-23
申请人： Min-Hwa Chi , Chih-Yuan Lu
发明人： Min-Hwa Chi , Chih-Yuan Lu
IPC分类号： H01L2120
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/10832 , H01L27/1203
摘要： A method for fabricating a DRAM cell, on a SOI layer, is described, featuring the incorporation of a two dimensional, trench capacitor structure, for increased DRAM cell signal, and the use of a polysilicon storage node structure to connect the SOI layer to the semiconductor substrate, to eliminate a floating body effect. A two dimensional trench is created by initially forming a vertical trench, through the SOI layer, through the underlying insulator layer, and into the semiconductor substrate. An isotropic etch is than performed to laterally remove a specific amount of insulator layer, exposed in the vertical trench, creating the lateral component of the two dimensional trench. A deposited polysilicon layer, coating the sides of the two dimensional trench, is used as the storage node structure, for the two dimensional, trench capacitor structure, while also connecting the SOI layer to the semiconductor substrate.
摘要翻译：描述了在SOI层上制造DRAM单元的方法，其特征在于结合用于增加的DRAM单元信号的二维沟槽电容器结构，以及使用多晶硅存储节点结构将SOI层连接到半导体衬底，消除浮体效应。通过初始形成穿过SOI层的垂直沟槽，穿过下面的绝缘体层并进入半导体衬底而形成二维沟槽。进行各向同性蚀刻以横向移除在垂直沟槽中暴露的特定量的绝缘体层，产生二维沟槽的横向分量。作为二维沟槽电容器结构的存储节点结构，同时也将SOI层与半导体基板连接，使用涂覆二维沟槽的侧面的沉积多晶硅层。

66. 发明授权

US6071774A Method for forming a capacitor with a multiple pillar structure 失效
标题翻译：一种形成具有多支柱结构的电容器的方法
公开(公告)号：US6071774A
公开(公告)日：2000-06-06
申请号：US121709
申请日：1998-07-24
申请人： Jan Mye Sung , Howard C. Kirsch , Chih-Yuan Lu
发明人： Jan Mye Sung , Howard C. Kirsch , Chih-Yuan Lu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10817 , H01L27/10852 , H01L28/92 , H01L28/84 , Y10S438/947 , Y10S438/968
摘要： The present invention provides a method for fabricating a multiple pillar shaped capacitor which has pillars of a smaller dimension than the resolution of the photolithography tool. The invention has two embodiments for forming the pillars and third embodiment for patterning a conductive layer into discrete bottom electrodes. The method begins by forming a conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller that the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars. The third embodiment uses two resist layers and a photo mask shifting (offset) technique to form small spaces between the electrodes. Lastly, a capacitor dielectric layer and a top electrode are formed over the bottom electrodes thereby completing the capacitor with a pillar structure.
摘要翻译：本发明提供一种制造多柱形电容器的方法，该多柱形电容器的尺寸小于光刻工具的分辨率。本发明具有用于形成支柱的两个实施例和用于将导电层图案化成离散底部电极的第三实施例。该方法开始于在第一平坦化层上形成导电层。对于第一实施例，使用具有间隔透明区域的图案的光刻掩模形成柱。间隔透明区域的尺寸和间隔开的透明区域之间的距离小于光刻工具的分辨率。用掩模形成间隔氧化物岛，并用作蚀刻掩模以与导电层形成间隔的柱。用于形成柱的第二实施例涉及使用小的硅化钛岛作为蚀刻掩模来限定柱。第三实施例使用两个抗蚀剂层和光掩模移位（偏移）技术在电极之间形成小的空间。最后，在底部电极上形成电容器电介质层和顶部电极，由此完成具有柱状结构的电容器。

67. 发明授权

US6057573A Design for high density memory with relaxed metal pitch 有权
标题翻译：设计用于高密度存储器，具有轻松的金属间距
公开(公告)号：US6057573A
公开(公告)日：2000-05-02
申请号：US313305
申请日：1999-05-17
申请人： Howard C. Kirsch , Chih-Yuan Lu
发明人： Howard C. Kirsch , Chih-Yuan Lu
IPC分类号： H01L23/522 , H01L23/528 , H01L27/105 , H01L27/108 , H01L21/8242
CPC分类号： H01L27/105 , H01L23/5221 , H01L23/5283 , H01L27/10805 , H01L2924/0002
摘要： A method and design for stitching polysilicon wordlines to straps formed of interconnected metal line segments formed in two or more metallization levels. Each strap comprises a continuous conductive metal line passing alternatively from one metal layer to another in a selected sequence. The sequence of segments in each strap alternates in phase with the sequence in next nearest neighbor straps but may be in phase with second nearest neighbor straps. Thereby the pitch of strap segments on each metallization level is at least twice that of the subjacent polysilicon wordlines. The total length of each metal in each strap is the same in all straps. This arrangement allows the use of metals having different resistivities in each strap with all the straps having identical overall resistance. The metals used in the two or more levels may also have different minimum design rules without compromising the identical overall performance of all the straps. In a second embodiment a method and design is described for doubling the length of polysilicon sub-wordlines in a sub-wordline memory array without reducing performance by connecting sub-wordline to sub-wordline decoders by metal straps connected to the sub-wordlines midpoints.
摘要翻译：一种用于将多晶硅字线拼接到由形成在两个或更多个金属化层级中的互连金属线段形成的带的方法和设计。每个带包括以选定的顺序交替地从一个金属层传递到另一个金属层的连续导电金属线。每个带中的段序列与下一个最近邻带中的序列相交，但是可以与第二最近邻带相同步。因此，每个金属化水平上的带段的间距至少是下面的多晶硅字线的两倍。每个皮带中的每个金属的总长度在所有带中是相同的。这种布置允许在每个带中使用具有不同电阻率的金属，其中所有带具有相同的整体电阻。在两个或更多个级别中使用的金属也可以具有不同的最小设计规则，而不会影响所有带的相同的整体性能。在第二实施例中，描述了一种方法和设计，用于使子字线存储器阵列中的多晶硅子字线的长度加倍，而不会通过连接到子字线中点的金属带将子字线连接到子字线解码器来降低性能。

68. 发明授权

US5759894A Method for forming a DRAM capacitor using HSG-Si 失效
标题翻译：使用HSG-Si形成DRAM电容器的方法
公开(公告)号：US5759894A
公开(公告)日：1998-06-02
申请号：US808338
申请日：1997-02-28
申请人： Horng-Huei Tseng , Chih-Yuan Lu
发明人： Horng-Huei Tseng , Chih-Yuan Lu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/92
摘要： A method for forming a DRAM capacitor using HSG-Si includes forming a dielectric layer over a substrate. A portion of the dielectric layer is removed to expose a contact area on the substrate. A polysilicon layer is then formed over the dielectric layer and in the first trench. Then, a hemispherical-grained silicon (HSG-Si) layer is formed on the polysilicon layer using an initial phase HSG-Si process, thereby forming a large number of silicon grains on the polysilicon layer. Next, nitrogen atoms are implanted into the polysilicon layer using the HSG-Si layer as a mask to form nitrogen regions in the polysilicon layer. The HSG-Si layer is then removed and the polysilicon layer is thermally oxidized. The nitrogen regions function as an anti-oxidation mask so that polysilicon-oxide regions are formed between the nitrogen regions in the polysilicon layer. Afterwards, an etching process is performed using the polysilicon-oxide regions as a mask so that the nitrogen regions and portions of the polysilicon layer beneath the nitrogen regions are removed. This etching step forms second trenches in the polysilicon layer between the polysilicon-oxide regions, which are subsequently removed. After removing the polysilicon-oxide regions, the polysilicon layer is patterned and etched to form a bottom electrode of the capacitor of the dynamic random access memory. The capacitor dielectric and the top electrode of the capacitor are then formed using conventional methods.
摘要翻译：使用HSG-Si形成DRAM电容器的方法包括在衬底上形成电介质层。去除介电层的一部分以露出衬底上的接触区域。然后在电介质层上和第一沟槽中形成多晶硅层。然后，使用初始相HSG-Si工艺在多晶硅层上形成半球状硅（HSG-Si）层，从而在多晶硅层上形成大量的硅晶粒。接下来，使用HSG-Si层作为掩模将氮原子注入到多晶硅层中，以在多晶硅层中形成氮区。然后去除HSG-Si层，并且多晶硅层被热氧化。氮区域用作抗氧化掩模，使得在多晶硅层中的氮区域之间形成多晶氧化物区域。然后，使用多晶硅氧化物区域作为掩模进行蚀刻处理，使得氮区域和氮区域下方的多晶硅层的部分被去除。该蚀刻步骤在多晶硅层之间形成第二沟槽，该多晶硅层随后被去除。在去除多晶硅氧化物区域之后，对多晶硅层进行图案化和蚀刻以形成动态随机存取存储器的电容器的底部电极。然后使用常规方法形成电容器电介质和电容器的顶部电极。

69. 发明授权

US5679589A FET with gate spacer 失效
标题翻译： FET带栅极间隔
公开(公告)号：US5679589A
公开(公告)日：1997-10-21
申请号：US866942
申请日：1992-04-03
申请人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78 , H01L21/28
CPC分类号： H01L29/66575 , H01L29/6656 , H01L29/6659 , H01L29/78
摘要： A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adjacent double or triple layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.
摘要翻译：公开了一种半导体集成电路结构及其制造方法。该结构包括具有相邻的双层或三层栅极间隔物的FET栅极。间隔物允许精细地定制具有深浅接合部分的轻掺杂漏极结型材。此外，自对准硅化物可以仅形成在深结部分上方，从而产生与源极和漏极的可靠的低接触电阻连接。

70. 发明授权

US5552620A Vertical transistor with high density DRAM cell and method of making 失效
标题翻译：具有高密度DRAM单元的垂直晶体管及其制造方法
公开(公告)号：US5552620A
公开(公告)日：1996-09-03
申请号：US428763
申请日：1995-04-24
申请人： Chih-Yuan Lu , Horng-Huei Tseng
发明人： Chih-Yuan Lu , Horng-Huei Tseng
IPC分类号： H01L27/108
CPC分类号： H01L27/10841 , Y10S257/90
摘要： There is shown a method for fabricating a vertical DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements and a capacitor. There is provided a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate. A pattern is formed of bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes so that it covers the gate dielectric and the field oxide isolation. A silicon nitride layer is formed over the doped polysilicon layer. Patterning and etching is done to the silicon nitride layer and doped polysilicon layer to form the opening for the capacitor node contact to the buried source/drain of the vertical field effect transistor (switching device for the storage signal) and establish said gate electrode in the hole and word line pattern over the field oxide insulator. A silicon oxide spacer is formed over the sidewalls of the silicon nitride and doped polysilicon layer. A capacitor is formed in and over the hole to complete the vertical DRAM cell.
摘要翻译：示出了制造垂直DRAM单元的方法，其包括具有栅电极和源极/漏极元件的电场效应晶体管和电容器。在硅衬底中提供了场氧化物隔离的图案，其中存在到硅衬底的开口图案。图案由位线和具有位于每个到所述硅衬底的每个开口内的孔的线的图案形成，孔和位线的线彼此垂直，并且线在所述硅衬底的计划位置处交叉垂直DRAM单元以与硅衬底的开口的图案形成。在孔的表面上形成栅极电介质。在孔内和上方形成掺杂多晶硅层，使其覆盖栅极电介质和场氧化物隔离。在掺杂多晶硅层上形成氮化硅层。对氮化硅层和掺杂多晶硅层进行图案化和蚀刻，以形成用于电容器节点接触到垂直场效应晶体管（用于存储信号的开关器件）的掩埋源极/漏极的开口，并在孔和字线图形在场氧化物绝缘体上。在氮化硅和掺杂多晶硅层的侧壁上形成氧化硅隔离物。在孔内和上方形成电容器以完成垂直DRAM单元。

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