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1. 发明授权

US5679589A FET with gate spacer 失效
标题翻译： FET带栅极间隔
公开(公告)号：US5679589A
公开(公告)日：1997-10-21
申请号：US866942
申请日：1992-04-03
申请人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78 , H01L21/28
CPC分类号： H01L29/66575 , H01L29/6656 , H01L29/6659 , H01L29/78
摘要： A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adjacent double or triple layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.
摘要翻译：公开了一种半导体集成电路结构及其制造方法。该结构包括具有相邻的双层或三层栅极间隔物的FET栅极。间隔物允许精细地定制具有深浅接合部分的轻掺杂漏极结型材。此外，自对准硅化物可以仅形成在深结部分上方，从而产生与源极和漏极的可靠的低接触电阻连接。

2. 发明授权

US5153145A FET with gate spacer 失效
标题翻译：带栅极间隔的FET
公开(公告)号：US5153145A
公开(公告)日：1992-10-06
申请号：US422834
申请日：1989-10-17
申请人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66575 , H01L29/6656 , H01L29/6659 , H01L29/78
摘要： A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adajcent double or triple-layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.

3. 发明授权

US5002898A Integrated-circuit device isolation 失效
标题翻译：集成电路器件隔离
公开(公告)号：US5002898A
公开(公告)日：1991-03-26
申请号：US423992
申请日：1989-10-19
申请人： Larry B. Fritzinger , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Larry B. Fritzinger , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/76 , H01L21/316 , H01L21/32 , H01L21/762
CPC分类号： H01L21/32 , H01L21/76202
摘要： In the manufacture of integrated-circuit semiconductor devices, prior to formation of a field oxide, a mask structure is provided on a silicon device area, comprising a pad oxide layer, a polysilicon buffer layer, a protective oxide layer, and a silicon nitride mask layer. Inclusion of the protective layer between polysilicon and silicon nitride layers prevents pad oxide failure and attendant substrate etching during strip-etching of the structure overlying the pad oxide.

4. 发明授权

US4935376A Making silicide gate level runners 失效
标题翻译：制作硅化物浇口水平赛跑者
公开(公告)号：US4935376A
公开(公告)日：1990-06-19
申请号：US420207
申请日：1989-10-12
申请人： Steven J. Hillenius , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Steven J. Hillenius , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L29/78 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/768
CPC分类号： H01L21/76889 , H01L21/28052 , H01L21/28123
摘要： Integrated circuits are fabricated with thick self-aligned silicide runners on the field oxide by etching back the first dielectric to expose patterned polysilicon on the field oxide and then forming a silicide on the patterned polysilicon.

5. 发明授权

US5821142A Method for forming a capacitor with a multiple pillar structure 失效
标题翻译：一种形成具有多支柱结构的电容器的方法
公开(公告)号：US5821142A
公开(公告)日：1998-10-13
申请号：US629158
申请日：1996-04-08
申请人： JanMye Sung , Howard C. Kirsch , Chih-Yuan Lu
发明人： JanMye Sung , Howard C. Kirsch , Chih-Yuan Lu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10817 , H01L27/10852 , H01L28/92 , H01L28/84 , Y10S438/947 , Y10S438/968
摘要： The present invention provides a method for fabricating a multiple pillar shaped capacitor which has pillars of a smaller dimension than the resolution of the photolithography tool. The invention has two embodiments for forming the pillars and third embodiment for patterning a conductive layer into discrete bottom electrodes. The method begins by forming a conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller then that of the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars. The third embodiment uses two resist layers and a photo mask shifting (offset) technique to form small spaces between the electrodes. Lastly, a capacitor dielectric layer and a top electrode are formed over the bottom electrodes thereby completing the capacitor with a pillar structure.
摘要翻译：本发明提供一种制造多柱形电容器的方法，该多柱形电容器的尺寸小于光刻工具的分辨率。本发明具有用于形成支柱的两个实施例和用于将导电层图案化成离散底部电极的第三实施例。该方法开始于在第一平坦化层上形成导电层。对于第一实施例，使用具有间隔透明区域的图案的光刻掩模形成柱。间隔开的透明区域的尺寸和间隔开的透明区域之间的距离小于光刻工具的分辨率的尺寸。用掩模形成间隔氧化物岛，并用作蚀刻掩模以与导电层形成间隔的柱。用于形成柱的第二实施例涉及使用小的硅化钛岛作为蚀刻掩模来限定柱。第三实施例使用两个抗蚀剂层和光掩模移位（偏移）技术在电极之间形成小的空间。最后，在底部电极上形成电容器电介质层和顶部电极，由此完成具有柱状结构的电容器。

6. 发明授权

US06180453B2 Method to fabricate a DRAM cell with an area equal to five times the minimum used feature, squared 有权
标题翻译：制造具有等于最小使用特征的五倍的面积的DRAM单元的方法
公开(公告)号：US06180453B2
公开(公告)日：2001-01-30
申请号：US09216794
申请日：1998-12-21
申请人： JanMye Sung , Chih-Yuan Lu
发明人： JanMye Sung , Chih-Yuan Lu
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10852 , H01L27/10873 , H01L28/91
摘要： A process for fabricating a DRAM cell, with an area equal to five times the minimum feature, squared, (5F2), has been developed. The process features the use of selectively formed, N+ single crystalline, silicon plugs, on underlying source/drain regions. The N+ single crystalline, silicon plugs, epitaxial deposited, are used to connect overlying crown shaped capacitor structures, to underlying source/drain region, as well as to connect a bit line metal structure, to another source/drain region.
摘要翻译：已经开发了制造具有等于最小特征的五倍的面积（5F2）的DRAM单元的工艺。该方法的特征在于在底层的源极/漏极区域上使用选择性形成的N +单晶硅插头。 N +单晶，硅插头，外延沉积，用于将覆盖的冠状电容器结构连接到下层源极/漏极区域，以及将位线金属结构连接到另一个源极/漏极区域。

7. 发明授权

US5943581A Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits 失效
标题翻译：制造用于高密度动态随机存取存储器（DRAM）电路的埋藏式电容器结构的方法
公开(公告)号：US5943581A
公开(公告)日：1999-08-24
申请号：US964808
申请日：1997-11-05
申请人： Chih-Yuan Lu , Janmye Sung
发明人： Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10858 , H01L27/10832
摘要： An improved DRAM cell using a novel buried reservoir capacitor is achieved. The method forms an array of N.sup.+ doped regions in a substrate. P-wells are formed in an epitaxy layer on the substrate. A field oxide (FOX) is formed surrounding the device areas aligned over the N.sup.+ regions. Holes are etched in the epi layer to the N.sup.+ regions, and a selective wet etch removes the N.sup.+ doped regions to form cavities. A thin dielectric layer is deposited on the cavity walls, and an N.sup.+ polysilicon layer is deposited and polished back to form the buried reservoir capacitors. The N.sup.+ polysilicon in the holes forms the capacitor node contacts for the FETs in the device areas. The array of DRAM cells is completed by growing a gate oxide, depositing and patterning a first polycide layer to form FET gate electrodes on the device areas over the capacitors, thereby providing increased capacitance while reducing the cell area. Lightly doped source/drain (LDD) areas, sidewall spacers and heavily doped source/drain contacts are formed for the FETs. A node strap is formed between one source/drain contact and the node contact to make good electrical contact. An insulating layer is deposited having bit line contact holes, and a second polycide layer is patterned to form the bit lines for the DRAM.
摘要翻译：实现了使用新颖的埋藏式电容器的改进的DRAM单元。该方法在衬底中形成N +掺杂区域的阵列。在衬底上的外延层中形成P阱。围绕在N +区域上排列的器件区域周围形成场氧化物（FOX）。将孔在外延层中蚀刻到N +区，并且选择性湿蚀刻去除N +掺杂区以形成空穴。在空腔壁上沉积薄的电介质层，并且沉积并抛光N +多晶硅层以形成埋藏的储存电容器。孔中的N +多晶硅形成器件区域中的FET的电容器节点接触。通过生长栅极氧化物，沉积和图案化第一多晶硅层以在电容器上的器件区域上形成FET栅电极来完成DRAM单元的阵列，从而在减小电池面积的同时提供增加的电容。形成用于FET的轻掺杂源极/漏极（LDD）区域，侧壁间隔物和重掺杂源极/漏极接触。节点带形成在一个源极/漏极接触点和节点接触点之间以形成良好的电接触。沉积具有位线接触孔的绝缘层，并且图案化第二多晶硅化物层以形成用于DRAM的位线。

8. 发明授权

US5792680A Method of forming a low cost DRAM cell with self aligned twin tub CMOS devices and a pillar shaped capacitor 失效
标题翻译：用自对准双槽CMOS器件和柱状电容器形成低成本DRAM单元的方法
公开(公告)号：US5792680A
公开(公告)日：1998-08-11
申请号：US756129
申请日：1996-11-25
申请人： Janmye Sung , Chih-Yuan Lu , Howard Clayton Kirsch
发明人： Janmye Sung , Chih-Yuan Lu , Howard Clayton Kirsch
IPC分类号： H01L21/8239 , H01L21/8242 , H01L27/108 , H01L21/8238
CPC分类号： H01L27/10852 , H01L27/1052 , H01L27/10817
摘要： The invention is a method of forming a reduced cost DRAM. The process has two embodiments for forming twin wells and two embodiments for forming pillar shaped capacitor electrodes. The twin well embodiments are simple low cost processes. The embodiments for forming the electrode pillars begin by forming a tungsten silicide conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller that the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. This first embodiment for fabricating the multiple pillar capacitor forms pillars of a smaller dimension than the resolution of the photolithography tool. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars.
摘要翻译：本发明是一种形成降低成本的DRAM的方法。该方法具有用于形成双阱的两个实施例和用于形成柱状电容器电极的两个实施例。双阱实施例是简单的低成本处理。用于形成电极柱的实施例开始于在第一平坦化层上形成硅化钨导电层。对于第一实施例，使用具有间隔透明区域的图案的光刻掩模形成柱。间隔透明区域的尺寸和间隔开的透明区域之间的距离小于光刻工具的分辨率。用掩模形成间隔氧化物岛，并用作蚀刻掩模以与导电层形成间隔的柱。用于制造多支柱电容器的第一实施例形成比光刻工具的分辨率小的尺寸的柱。用于形成柱的第二实施例涉及使用小的硅化钛岛作为蚀刻掩模来限定柱。

9. 发明授权

US4999317A Metallization processing 失效
标题翻译：金属化处理
公开(公告)号：US4999317A
公开(公告)日：1991-03-12
申请号：US414888
申请日：1989-09-29
申请人： Chih-Yuan Lu , Janmye Sung , Yiu M. Wong
发明人： Chih-Yuan Lu , Janmye Sung , Yiu M. Wong
IPC分类号： H01L21/28 , H01L21/285 , H01L23/482
CPC分类号： H01L23/4824 , H01L2924/0002
摘要： When forming a metallization layer in integrated-circuit semiconductor device fabrication, metal such as tungsten, for example, adheres poorly to a dielectric such as, e.g., silicon oxide, and tends to flake off from wafer areas not covered by a glue layer. Processing of the invention prevents such flaking by, first, removing the dielectric from the back side, edge, and "clip-mark" areas of the wafer and, second, depositing a glue layer on remaining dielectric on the face of the wafer. Removal of dielectric material is by etching in the presence of a protective layer on the face of the wafer.

10. 发明授权

US4952524A Semiconductor device manufacture including trench formation 失效
标题翻译：半导体器件制造包括沟槽形成
公开(公告)号：US4952524A
公开(公告)日：1990-08-28
申请号：US347975
申请日：1989-05-05
申请人： Kuo-Hua Lee , Chih-Yuan Lu
发明人： Kuo-Hua Lee , Chih-Yuan Lu
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/316 , H01L21/762
CPC分类号： H01L21/31604 , H01L21/31051 , H01L21/31055 , H01L21/76229
摘要： A trench which provides electrical isolation between transistors on an integrated circuit substrate is described. The trench is lined with a diffusion barrier, typically a thermal oxide followed by a thermal stress relief layer, typically formed from TEOS. Then a filler material, typically BPTEOS, is deposited to fill the trench and cover the upper surface of the wafer. The filler material is heated to make it flow. Next the outer surface of the flowed filler material is next subjected to an etch-back which makes the top surface of the filled trench protrude slightly above the upper surface of the substrate. The resulting trench contains the diffusion barrier layer, the thermal stress relief layer, and the filler material. The filler material and the thermal stress relief layer will soften during subsequent heat treatments of the wafer, thus relieving thermal stresses, and preventing the occurrence of defects and dislocations within the wafer.

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