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61. 发明授权

US06583018B1 Method of ion implantation 失效
标题翻译：离子注入方法
公开(公告)号：US06583018B1
公开(公告)日：2003-06-24
申请号：US09719089
申请日：2001-02-05
申请人： Yasuhiko Matsunaga , Majeed Ali Foad
发明人： Yasuhiko Matsunaga , Majeed Ali Foad
IPC分类号： H01L21331
CPC分类号： H01L21/26506 , H01L21/26513
摘要： An ion implantation method which can accurately control the effective dose amount even in ion implantation at a very low energy. This ion implantation method comprises the steps of carrying out preamorphization ion implantation for a semiconductor substrate in an ion implantation apparatus; then cleaning the surface of semiconductor substrate in a cleaning apparatus so as to eliminate an oxidized film; and thereafter carrying out ion implantation again in the ion implantation apparatus under a low implantation energy so as to form a shallow junction in the semiconductor substrate. As a consequence, the influence of the oxidized film formed by preamorphization ion implantation can be suppressed, whereby the effective dose can be controlled accurately.
摘要翻译：一种即使在非常低的能量下进行离子注入也能够精确地控制有效剂量的离子注入方法。该离子注入方法包括在离子注入装置中对半导体衬底进行预变质离子注入的步骤; 然后在清洁装置中清洗半导体衬底的表面以消除氧化膜; 然后在低注入能量下在离子注入装置中再次进行离子注入，以在半导体衬底中形成浅结。结果，可以抑制通过前变质离子注入形成的氧化膜的影响，从而可以准确地控制有效剂量。

62. 发明授权

US08818355B2 Wireless cell monitoring method, its device, and its program 有权
标题翻译：无线电池监控方法，其设备及其程序
公开(公告)号：US08818355B2
公开(公告)日：2014-08-26
申请号：US12531103
申请日：2008-02-26
申请人： Kosei Kobayashi , Yasuhiko Matsunaga
发明人： Kosei Kobayashi , Yasuhiko Matsunaga
IPC分类号： H04W24/08
CPC分类号： H04W24/08
摘要： In a wireless cell, the potential deterioration in quality is efficiently detected when the indication of abnormalities is weak. Provided are a step of calculating one or more radio qualities for each coverage area of a wireless cell; a step of measuring one or more network statistical qualities for each coverage area of the wireless cell; a step of making a pair of each network statistical quality and one or more radio qualities for each coverage area of each wireless cell; and a step of calculating, based on the pairs of each network statistical quality and one or more radio qualities for the coverage areas of the wireless cells, the correlation between each network statistical quality and one or more radio qualities.
摘要翻译：在无线小区中，当异常指示弱时，可以有效地检测质量的潜在恶化。提供了对无线小区的每个覆盖区域计算一个或多个无线电质量的步骤; 测量无线小区的每个覆盖区域的一个或多个网络统计特性的步骤; 为每个无线小区的每个覆盖区域提供一对每个网络统计质量和一个或多个无线电质量的步骤; 以及基于每个网络统计质量的对和无线小区的覆盖区域的一个或多个无线电质量来计算每个网络统计质量与一个或多个无线电质量之间的相关性的步骤。

63. 发明授权

US08525246B2 Semiconductor storage device and method of manufacturing the same 有权
标题翻译：半导体存储装置及其制造方法
公开(公告)号：US08525246B2
公开(公告)日：2013-09-03
申请号：US12724802
申请日：2010-03-16
申请人： Yoshiko Kato , Hiroyuki Kutsukake , Kikuko Sugimae , Yasuhiko Matsunaga
发明人： Yoshiko Kato , Hiroyuki Kutsukake , Kikuko Sugimae , Yasuhiko Matsunaga
IPC分类号： H01L29/76
CPC分类号： H01L27/11521
摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a first device isolation/insulation film formed in a trench, the trench formed in the semiconductor layer, with a first direction taken as a longitudinal direction; a device formation region formed by separating the semiconductor layer by the first device isolation/insulation film with the first direction taken as a longitudinal direction; and a memory transistor disposed on the device formation region. The first device isolation/insulation film and the device formation region have an impurity of a first conductivity type. An impurity concentration of the impurity of the first conductivity type in the first device isolation/insulation film is higher than that in the device formation region.
摘要翻译：非易失性半导体存储器件包括：半导体衬底; 形成在半导体衬底上的半导体层; 形成在沟槽中的第一器件隔离/绝缘膜，形成在半导体层中的沟槽，第一方向作为纵向方向; 通过第一装置隔离/绝缘膜将第一方向作为纵向方向分离半导体层而形成的器件形成区域; 以及设置在器件形成区域上的存储晶体管。第一器件隔离/绝缘膜和器件形成区具有第一导电类型的杂质。第一器件隔离/绝缘膜中的第一导电类型的杂质的杂质浓度高于器件形成区域中的杂质浓度。

64. 发明授权

US08315631B2 Radio-resource management system and method thereof, and management apparatus, base station and terminal to be employed for it 有权
公开(公告)号：US08315631B2
公开(公告)日：2012-11-20
申请号：US12882495
申请日：2010-09-15
申请人： Yasuhiko Matsunaga
发明人： Yasuhiko Matsunaga
IPC分类号： H04W36/00
CPC分类号： H04W28/16 , H04W16/14 , H04W24/10 , H04W36/14 , H04W36/22 , H04W52/18 , H04W52/241 , H04W68/005
摘要： Terminals and base stations belonging to service areas 100 to 102 of plural radio operators periodically measure a radio-link quality and an availability ratio of a radio link to notify them to a radio-resource management server 40. The server 40 alters a frequency of the base station, and a transmitted-power quantity of the base station and the terminal based on these measured results to improve the radio-link quality, and reduces interference with a neighboring radio system. When a load is concentrated on a network of a specific radio operator, an instruction of handover is given to the terminal from the server 40 to realize a load distribution within the radio operator, and between the radio operators. When the server 40 detects excessive radio interference between the radio operators, it notifies occurrence of a fault, an interference quantity, a quantity of the transmitted power that the base station should attenuate, and the frequency that the base station should alter to the above radio operator that becomes an interference source.

65. 发明授权

US08169927B2 Configuration management method and configuration management system of wireless access network, and wireless access network management device 有权
标题翻译：无线接入网络的配置管理方法和配置管理系统，以及无线接入网管理设备
公开(公告)号：US08169927B2
公开(公告)日：2012-05-01
申请号：US12302147
申请日：2007-05-29
申请人： Yasuhiko Matsunaga
发明人： Yasuhiko Matsunaga
IPC分类号： H04L12/26
CPC分类号： H04W28/08 , H04W16/18 , H04W24/02 , H04W88/12
摘要： A configuration of a wireless cell contained by a wireless network control station in a wireless access network is optimized to efficiently achieve leveling of a processing load in the wireless network control station. A wireless access network management device inputs input information including position information of a wireless cell, traffic demand of each wireless cell, location registration demand of each wireless cell, handover demand with respect to each adjacent wireless cells of each wireless cell, and internal processing time required by a wireless network control station for traffic processing, location registration processing, and handover processing. Then, a wireless cell group to be controlled by a wireless network control station is selected based on the input information so that processing loads of a plurality of wireless network control station are leveled.
摘要翻译：对无线接入网络中的无线网络控制站所包含的无线小区的配置进行优化，以有效地实现无线网络控制站中的处理负载的调平。无线接入网络管理设备输入包括无线小区的位置信息，每个无线小区的业务需求，每个无线小区的位置登记需求，相对于每个无线小区的每个相邻无线小区的切换需求的输入信息，以及内部处理时间由无线网络控制站要求用于业务处理，位置注册处理和切换处理。然后，基于输入信息选择要由无线网络控制站控制的无线小区组，使得多个无线网络控制站的处理负载被调平。

66. 发明申请

US20120099374A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120099374A1
公开(公告)日：2012-04-26
申请号：US13277623
申请日：2011-10-20
申请人： Yasuhiko MATSUNAGA
发明人： Yasuhiko MATSUNAGA
IPC分类号： G11C16/04
CPC分类号： H01L27/11529 , H01L23/485 , H01L27/0207 , H01L27/11519 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory device includes a substrate including device regions extending in a first direction, a memory cell array region including a plurality of memory cells disposed on the device regions, bit lines extending in the first direction, a sense amplifier circuit connected to ends of the bit lines, and bit line contacts connecting device regions to bit lines. The memory cell array region includes first to N-th regions where N is an integer of two or more, and a K-th region is located at a greater distance from the sense amplifier circuit than a (K−1)-th region, where K is an arbitrary integer of 2 to N. Contact resistance of the bit line contacts in the K-th region is lower than contact resistance of the bit line contacts in the (K−1)-th region, each device region having constant width in the memory cell array region.
摘要翻译：一种非易失性半导体存储器件，包括：基板，包括沿第一方向延伸的器件区域;存储单元阵列区域，包括设置在器件区域上的多个存储单元;沿第一方向延伸的位线;连接到位线和位线接触将器件区域连接到位线。存储单元阵列区域包括第一至第N区域，其中N是两个或更多个的整数，并且第K个区域位于距离读出放大器电路比第（K-1）个区域更大的距离处，其中K是2至N的任意整数。在第K区中位线接触的接触电阻低于第（K-1）区中的位线接触的接触电阻，每个器件区具有恒定存储单元阵列区域的宽度。

67. 发明授权

US08134198B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US08134198B2
公开(公告)日：2012-03-13
申请号：US11563069
申请日：2006-11-24
申请人： Takeshi Kamigaichi , Yasuhiko Matsunaga
发明人： Takeshi Kamigaichi , Yasuhiko Matsunaga
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes active regions . . . AAj−1, AAj, AAj−1, . . . formed in a semiconductor substrate; a plurality of word lines WL0, WL1, . . . in the row direction; memory cell transistors, each including a floating gate provided on the semiconductor substrate via a tunneling insulating film, an inter-gate insulating film disposed on the floating gate, and a control gate disposed on the inter-gate insulating film, disposed on intersections of word lines and active regions; select gate lines SGD in the row direction; bit line contacts CB disposed on the active regions; and a plurality of bit lines in the column direction and connected to the active regions via the bit line contacts; and the bit line contacts are formed by forming an electrode material for the bit line contacts in lines in the row direction and cutting the electrode material for each of the bit lines to avoid contact-failure of bit line contacts CB.
摘要翻译：非易失性半导体存储器包括有源区域。。。 AAj-1，AAj，AAj-1，。。形成在半导体衬底中; 多个字线WL0，WL1，...。。。在行方向存储单元晶体管，每个包括通过隧道绝缘膜设置在半导体衬底上的浮置栅极，设置在浮置栅极上的栅极间绝缘膜，以及设置在栅极间绝缘膜上的控制栅极，设置在字的交叉点上线和活动区域; 在行方向上选择栅极线SGD; 布置在有源区上的位线触点CB; 以及在列方向上的多个位线，并且经由位线触点连接到有源区; 并且通过在行方向上形成用于位线接触的电极材料并切割每个位线的电极材料来形成位线触点，以避免位线触点CB的接触故障。

68. 发明申请

US20100314677A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100314677A1
公开(公告)日：2010-12-16
申请号：US12724802
申请日：2010-03-16
申请人： Yoshiko KATO , Hiroyuki Kutsukake , Kikuko Sugimae , Yasuhiko Matsunaga
发明人： Yoshiko KATO , Hiroyuki Kutsukake , Kikuko Sugimae , Yasuhiko Matsunaga
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11521
摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a first device isolation/insulation film formed in a trench, the trench formed in the semiconductor layer, with a first direction taken as a longitudinal direction; a device formation region formed by separating the semiconductor layer by the first device isolation/insulation film with the first direction taken as a longitudinal direction; and a memory transistor disposed on the device formation region. The first device isolation/insulation film and the device formation region have an impurity of a first conductivity type. An impurity concentration of the impurity of the first conductivity type in the first device isolation/insulation film is higher than that in the device formation region.
摘要翻译：非易失性半导体存储器件包括：半导体衬底; 形成在半导体衬底上的半导体层; 形成在沟槽中的第一器件隔离/绝缘膜，形成在半导体层中的沟槽，第一方向作为纵向方向; 通过第一装置隔离/绝缘膜将第一方向作为纵向方向分离半导体层而形成的器件形成区域; 以及设置在器件形成区域上的存储晶体管。第一器件隔离/绝缘膜和器件形成区具有第一导电类型的杂质。第一器件隔离/绝缘膜中的第一导电类型的杂质的杂质浓度高于器件形成区域中的杂质浓度。

69. 发明申请

US20100238733A1 NAND FLASH MEMORY 有权
标题翻译： NAND闪存
公开(公告)号：US20100238733A1
公开(公告)日：2010-09-23
申请号：US12727817
申请日：2010-03-19
申请人： Koichi FUKUDA , Yasuhiko Matsunaga
发明人： Koichi FUKUDA , Yasuhiko Matsunaga
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/3436 , G11C11/5621
摘要： A NAND flash memory includes a NAND string and a control circuit, wherein in a write operation, the control circuit applies a writing voltage between a control gate of a selected memory cell to be written and a semiconductor well, and after the write operation and before performing a verification read operation of verifying whether data has been written into the selected memory cell, the control circuit performs a de-trapping operation, in which a first voltage of a same potential as that of the semiconductor well or a same polarity as that of the writing voltage is applied to the control gate of the selected memory cell and in which a second voltage of a same polarity as that of the writing voltage and larger than the first voltage as an absolute value is applied to a control gate of unselected memory cells not to be written.
摘要翻译： NAND闪速存储器包括NAND串和控制电路，其中在写入操作中，控制电路在要写入的所选存储单元的控制栅极和半导体阱之间以及在写入操作之后和之前施加写入电压执行验证数据是否被写入所选择的存储单元的验证读取操作，控制电路执行解除捕获操作，其中与半导体阱具有相同电位的第一电压或与写入电压被施加到所选择的存储单元的控制栅极，其中与写入电压相同极性的第二电压和大于作为绝对值的第一电压的第二电压被施加到未选择存储单元的控制栅极不写

70. 发明授权

US07772102B2 Nonvolatile semiconductor memory and fabrication method for the same 有权
标题翻译：非易失性半导体存储器及其制造方法相同
公开(公告)号：US07772102B2
公开(公告)日：2010-08-10
申请号：US12480383
申请日：2009-06-08
申请人： Yasuhiko Matsunaga
发明人： Yasuhiko Matsunaga
IPC分类号： H01L21/3205
CPC分类号： H01L27/115 , H01L27/11526 , H01L27/11529
摘要： A nonvolatile semiconductor memory that allows simultaneous implementation of high performance transistors in a low-voltage circuit region and transistors with high withstand voltages in a high-voltage circuit region. The nonvolatile semiconductor memory includes a cell array region that comprises aligned memory cell transistors, each including a control gate electrode, which includes a metal silicide film, an inter-gate insulating film below the control gate electrode, a floating gate electrode below the inter-gate insulating film, and a tunnel insulating film under the floating gate electrode; a high-voltage circuit region arranged in a periphery of the cell array region and including a high voltage transistor, which includes a first gate insulating film thicker than the tunnel insulating film; and a low-voltage circuit region that is arranged in a different position than the high-voltage circuit region arranged in the periphery of the cell array region and that includes a low-voltage transistor, which includes a gate electrode and a second gate insulating film thinner than the first gate insulating film below the gate electrode.
摘要翻译：一种非易失性半导体存储器，其允许在高压电路区域中同时实现低电压电路区域中的高性能晶体管和在高压电路区域中具有高耐受电压的晶体管。非易失性半导体存储器包括：单元阵列区域，其包括排列的存储单元晶体管，每个存储单元晶体管包括控制栅电极，其包括金属硅化物膜，位于控制栅极电极下方的栅极间绝缘膜，栅极绝缘膜和在浮栅电极下方的隧道绝缘膜; 布置在电池阵列区域的外围并包括高压晶体管的高压电路区域，其包括比隧道绝缘膜厚的第一栅极绝缘膜; 以及低压电路区域，其布置在与布置在电池阵列区域周围的高电压电路区域不同的位置，并且包括低电压晶体管，该低压晶体管包括栅极电极和第二栅极绝缘膜比栅电极下方的第一栅绝缘膜薄。

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