会员体验
专利管家（专利管理）
工作空间（专利管理）
风险监控（情报监控）
数据分析（专利分析）
侵权分析（诉讼无效）
联系我们
交流群
官方交流：
QQ群： 891211   
微信请扫码    >>>
现在联系顾问~
下载
著录项
PDF全文
热词
    • 63. 发明授权
      US5847409A Semiconductor device with superlattice-structured graded buffer layer and fabrication method thereof 失效
    • Semiconductor device with superlattice-structured graded buffer layer and fabrication method thereof
    • 具有超晶格结构的渐变缓冲层的半导体器件及其制造方法
    • US5847409A
    • 1998-12-08
    • US651787
    • 1996-05-24
    • Tatsuo Nakayama
    • Tatsuo Nakayama
    • H01L29/872 , H01L21/203 , H01L21/335 , H01L21/338 , H01L29/15 , H01L29/47 , H01L29/778 , H01L29/812 , H01L31/0328
    • H01L29/66462 , H01L29/155 , H01L29/7783
    • A semiconductor device that enables to prevent the electron transport property of a semiconductor active layer from degrading even if a semiconductor compositionally-graded buffer layer is used. This device contains a semiconductor substrate, a semiconductor active layer lattice-mismatched with the substrate, and a semiconductor compositionally-graded buffer layer formed between the substrate and the active layer. The compositionally-graded buffer layer has a semiconductor superlattice structure including first semiconductor sublayers and second semiconductor sublayers that are alternately stacked in a direction perpendicular to the substrate. Each of the first sublayers is made of a first semiconductor material. Each of the second sublayers is made of a second semiconductor material different in composition from the first semiconductor material. The lattice constant of the first and second sublayers decreases or increases stepwise from a side near the substrate and the other side near the active layer. The lattice constant of any one of the second sublayers may be larger than that of an adjacent one of the first sublayers and is smaller than that of another adjacent one of the first sublayers.
    • 即使使用半导体组成梯度缓冲层，也能够防止半导体活性层的电子传输性降低的半导体装置。 该器件包含半导体衬底，与衬底晶格失配的半导体有源层以及形成在衬底和有源层之间的半导体组成渐变缓冲层。 组成梯度缓冲层具有半导体超晶格结构，其包括在垂直于衬底的方向上交替堆叠的第一半导体子层和第二半导体子层。 每个第一子层由第一半导体材料制成。 每个第二子层由与第一半导体材料组成不同的第二半导体材料制成。 第一和第二子层的晶格常数从基板附近的一侧和活性层附近的另一侧逐步减小或增加。 第二子层中的任一个的晶格常数可以大于第一子层中的相邻层的晶格常数，并且小于第一子层中的另一相邻层之间的晶格常数。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 64. 发明授权
      US5557994A Ratchet handle with torque adjustment 失效
    • Ratchet handle with torque adjustment
    • 棘轮手柄带扭矩调节
    • US5557994A
    • 1996-09-24
    • US503436
    • 1995-07-17
    • Tatsuo Nakayama
    • Tatsuo Nakayama
    • B25B13/46 , B25B23/142
    • B25B13/461 , B25B13/463 , B25B23/1427
    • An adjustable torque ratchet wrench has a ratchet gear to be meshed with a ratchet pawl that restrains movement of the ratchet gear when a handle is rotated. The ratchet gear includes a shaft connected to a removeable fitting for engaging a bolt or the like to be tightened. The ratchet pawl is mounted on a moveable ratchet pawl block. The ratchet pawl block and the ratchet pawl are urged toward the ratchet gear by an adjustable spring assembly. The user selects a limiting torque using an adjustment means. When the limiting torque is achieved, the force of the spring is overcome and the ratchet pawl disengages from the ratchet gear as the ratchet pawl block slides in the direction of the spring. No further tightening of the bolt may then take place. Embodiments disclosed use varied spring types including disc springs, flat springs, coil springs, loop springs and a series of flat, overlapping springs.An embodiment having a piezoelectric element for detecting the amount of torque and transmitting the value as an electrical signal to assist the operator in knowing how much torque has been applied. A display provides real time monitoring of the tightening process.
    • 可调扭矩棘轮扳手具有与棘爪啮合的棘轮，当棘轮旋转时，该棘爪限制棘轮的运动。 棘轮包括连接到可拆卸配件的轴，用于接合待紧固的螺栓等。 棘爪被安装在可动棘爪块上。 棘爪棘爪和棘爪通过可调节的弹簧组件被推向棘齿。 用户使用调整装置选择限制转矩。 当实现限制转矩时，弹簧的力被克服，并且随着棘爪棘爪块沿弹簧的方向滑动，棘爪与棘轮脱离啮合。 然后可能不再进一步拧紧螺栓。 所公开的实施例使用各种弹簧类型，包括碟形弹簧，扁平弹簧，螺旋弹簧，环弹簧和一系列平坦重叠的弹簧。 具有用于检测扭矩量并将该值作为电信号传输以帮助操作者知道已经施加了多少扭矩的压电元件的实施例。 显示屏提供对紧固过程的实时监控。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 66. 发明授权
      US08659055B2 Semiconductor device, field-effect transistor, and electronic device 有权
    • Semiconductor device, field-effect transistor, and electronic device
    • 半导体器件，场效应晶体管和电子器件
    • US08659055B2
    • 2014-02-25
    • US13497557
    • 2010-06-16
    • Yasuhiro Okamoto , Kazuki Ota , Takashi Inoue , Hironobu Miyamoto , Tatsuo Nakayama , Yuji Ando
    • Yasuhiro Okamoto , Kazuki Ota , Takashi Inoue , Hironobu Miyamoto , Tatsuo Nakayama , Yuji Ando
    • H01L29/66 , H01L21/336
    • H01L29/7813 , H01L29/1054 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/267 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/66734
    • Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon.A semiconductor device includes a substrate 1, a first n-type semiconductor layer 2, a p-type semiconductor layer 3, a second n-type semiconductor layer 4, a drain electrode 13, a source electrode 11, a gate electrode 12, and a gate insulation film 21, wherein the first n-type semiconductor layer 2, the p-type semiconductor layer 3, and the second n-type semiconductor layer 4 are laminated on the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 2. The source electrode 11 is in ohmic-contact with the second n-type semiconductor layer 4. An opening portion to be filled or a notched portion that extends from an upper surface of the second n-type semiconductor layer 4 to an upper part of the first n-type semiconductor layer 2 is formed at a part of the p-type semiconductor layer 3 and a part of the second n-type semiconductor layer 4. The gate electrode 12 is in contact with an upper surface of the first n-type semiconductor layer 2, side surfaces of the p-type semiconductor layer 3, and side surfaces of the second n-type semiconductor layer 4 at inner surfaces of the opening portion to be filled or a surface of the notched portion via the gate insulation film 21. The p-type semiconductor layer 3 has a positive polarization charge at a first n-type semiconductor layer 2 side in a state where a voltage is applied to none of the electrodes.
    • 提供能够抑制穿通现象发生的半导体装置。 半导体器件包括衬底1，第一n型半导体层2，p型半导体层3，第二n型半导体层4，漏极13，源电极11，栅电极12和 栅极绝缘膜21，其中第一n型半导体层2，p型半导体层3和第二n型半导体层4依次层压在基板1上。 漏电极13与第一n型半导体层2欧姆接触。源电极11与第二n型半导体层4欧姆接触。要填充的开口部分或延伸的缺口部分 从第二n型半导体层4的上表面到第一n型半导体层2的上部形成在p型半导体层3的一部分上，第二n型半导体层的一部分 栅电极12与第一n型半导体层2的上表面，p型半导体层3的侧表面和第二n型半导体层4的内表面的侧表面接触 待填充的开口部分或经由栅极绝缘膜21的切口部分的表面。在施加电压的状态下，p型半导体层3在第一n型半导体层2侧具有正极化电荷 没有电极。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 68. 发明申请
      US20130113028A2 SEMICONDUCTOR DEVICE AND FIELD EFFECT TRANSISTOR 有权
    • SEMICONDUCTOR DEVICE AND FIELD EFFECT TRANSISTOR
    • 半导体器件和场效应晶体管
    • US20130113028A2
    • 2013-05-09
    • US13393002
    • 2010-06-23
    • Hironobu MIYAMOTO , Yasuhiro OKAMOTO , Yuji ANDO , Tatsuo NAKAYAMA , Takashi INOUE , Kazuki OTA , Kazuomi ENDO
    • Hironobu MIYAMOTO , Yasuhiro OKAMOTO , Yuji ANDO , Tatsuo NAKAYAMA , Takashi INOUE , Kazuki OTA , Kazuomi ENDO
    • H01L29/78
    • H01L29/8122 , H01L29/0657 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/7809 , H01L29/7812 , H01L29/7813 , H01L29/8128
    • A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.
    • 半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层 型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。 漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。 栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面 第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。 第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
每页展示10个专利
每页展示10个专利
每页展示20个专利
每页展示50个专利
每页展示100个专利

IPRDB

最新中国发明专利 最新美国发明专利 技术领域 专利库 专利分类库 国际专利分类库

热门服务

会员版试用 API 数据接口 找代理 知嘟嘟专利交易 排行榜 大学排行榜 专利百科

关于我们

平台介绍 战略合作 网站地图

友情链接

知嘟嘟专利交易 国家知识产权局 中国商标网

联系方式


©2019-2023 上海吉码数字技术有限公司 版权所有，并保留所有权利 沪ICP备20016256号-6 沪公网安备31011702005475号