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1. 发明申请

US20130113028A2 SEMICONDUCTOR DEVICE AND FIELD EFFECT TRANSISTOR 有权
标题翻译：半导体器件和场效应晶体管
公开(公告)号：US20130113028A2
公开(公告)日：2013-05-09
申请号：US13393002
申请日：2010-06-23
申请人： Hironobu MIYAMOTO , Yasuhiro OKAMOTO , Yuji ANDO , Tatsuo NAKAYAMA , Takashi INOUE , Kazuki OTA , Kazuomi ENDO
发明人： Hironobu MIYAMOTO , Yasuhiro OKAMOTO , Yuji ANDO , Tatsuo NAKAYAMA , Takashi INOUE , Kazuki OTA , Kazuomi ENDO
IPC分类号： H01L29/78
CPC分类号： H01L29/8122 , H01L29/0657 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/7809 , H01L29/7812 , H01L29/7813 , H01L29/8128
摘要： A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.
摘要翻译：半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。

2. 发明申请

US20120217547A1 FIELD EFFECT TRANSISTOR WITH REDUCED GATE LEAKAGE CURRENT 有权
标题翻译：具有降低栅极泄漏电流的场效应晶体管
公开(公告)号：US20120217547A1
公开(公告)日：2012-08-30
申请号：US13468373
申请日：2012-05-10
申请人： Yuji ANDO , Hironobu MIYAMOTO , Tatsuo NAKAYAMA , Yasuhiro OKAMOTO , Takashi INOUE , Yasuhiro MURASE , Kazuki OTA , Akio WAKEJIMA , Naotaka KURODA
发明人： Yuji ANDO , Hironobu MIYAMOTO , Tatsuo NAKAYAMA , Yasuhiro OKAMOTO , Takashi INOUE , Yasuhiro MURASE , Kazuki OTA , Akio WAKEJIMA , Naotaka KURODA
IPC分类号： H01L29/778
CPC分类号： H01L29/7787 , H01L29/2003
摘要： Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0≦y≦1); a carrier supply layer 13 composed of AlxGa1-xN (0≦x≦1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x
摘要翻译：公开了一种HJFET 110，其包括：由In y Ga 1-y N（0＆lt; n 1; y＆n 1; 1）构成的沟道层12; 载体供给层13由Al x Ga 1-x N（0＆lt; n 1; x＆n 1; 1）组成，载流子供给层13设置在沟道层12上并且包括至少一个p型层; 以及源极电极15S，漏极电极15D和栅极电极17，其通过p型层面对沟道层12，并且设置在载流子供给层13上。满足以下关系式：5.6×10 11× NA×＆eegr×T [cm-2] <5.6×1013x，其中x表示所述载体供给层的Al组成比，t表示所述p型层的厚度，NA表示杂质浓度，＆eegr; 表示活化比。

3. 发明申请

US20120319165A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120319165A1
公开(公告)日：2012-12-20
申请号：US13477498
申请日：2012-05-22
申请人： Tatsuo NAKAYAMA
发明人： Tatsuo NAKAYAMA
IPC分类号： H01L29/78 , H01L21/283 , H01L29/205
CPC分类号： H01L29/7787 , H01L21/28264 , H01L29/2003 , H01L29/4236 , H01L29/518 , H01L29/66462
摘要： Object of the invention is to reduce the on resistance between source and drain of a nitride semiconductor device. Between a nitride semiconductor layer lying between source and drain regions and a nitride semiconductor layer serving as an underlying layer, formed is a material having an electron affinity greater than that of these nitride semiconductor layers and having a lattice constant greater than that of the nitride semiconductor layer serving as an underlying layer. As a result, an electron density distribution of a channel formed below a gate insulating film and that of a two-dimensional electron gas formed in a region other than the gate portion, when a gate voltage is applied, can be made closer in the depth direction, leading to reduction in on resistance.
摘要翻译：本发明的目的是减少氮化物半导体器件的源极和漏极之间的导通电阻。在位于源极和漏极区域之间的氮化物半导体层和用作下层之间的氮化物半导体层之间形成的电子亲和力大于这些氮化物半导体层的电子亲和力，并具有大于氮化物半导体的晶格常数的晶格常数层作为底层。结果，在施加栅极电压时，形成在栅极绝缘膜下面的沟道的电子密度分布和形成在栅极部分以外的区域中的二维电子气的电子密度分布可以在深度上更接近方向，导致电阻降低。

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