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61. 发明申请

US20050009337A1 [METAL SILICIDE STRUCTURE AND METHOD OF FORMING THE SAME] 审中-公开
标题翻译： [金属硅化物结构及其形成方法]
公开(公告)号：US20050009337A1
公开(公告)日：2005-01-13
申请号：US10604835
申请日：2003-08-21
申请人： Hung-Wei Liu , Kuang-Chao Chen , Hsueh-Hao Shih
发明人： Hung-Wei Liu , Kuang-Chao Chen , Hsueh-Hao Shih
IPC分类号： H01L21/265 , H01L21/285 , H01L21/44
CPC分类号： H01L21/28518
摘要： A method of forming a suicide layer is described. A silicon layer is provided. Ions are introduced in the silicon layer. A metal layer is formed on the silicon layer. An annealing process is performed so that the silicon layer reacts with the metal layer to form the metal silicide layer. Thereafter, the unreacted metal layer is removed. The uniformity of the grain size and the grain distribution of the metal silicide layer are improved by introducing the ions in the silicon layer before performing the annealing process, so that sheet resistance of the metal silicide layer is reduced.
摘要翻译：描述了形成硅化物层的方法。提供硅层。硅在硅层中引入了离子。在硅层上形成金属层。执行退火处理，使得硅层与金属层反应以形成金属硅化物层。之后，除去未反应的金属层。在进行退火处理之前，通过在硅层中引入离子来改善金属硅化物层的晶粒尺寸和晶粒分布的均匀性，从而降低金属硅化物层的薄层电阻。

62. 发明授权

US06824452B1 Polishing pad and process of chemical mechanical use thereof 有权
标题翻译：抛光垫及其化学机械使用过程
公开(公告)号：US06824452B1
公开(公告)日：2004-11-30
申请号：US10605425
申请日：2003-09-30
申请人： Yung-Tai Hung , Yuhturng Liu , Hsueh-Hao Shih , Kuang-Chao Chen
发明人： Yung-Tai Hung , Yuhturng Liu , Hsueh-Hao Shih , Kuang-Chao Chen
IPC分类号： B24B100
CPC分类号： B24B37/24 , B24B37/042 , B24D3/32 , B24D13/147
摘要： A chemical mechanical polishing to polish a substrate having a layer to be polished thereon is described. A pre-polishing process is performed using a softer polishing pad to remove partially raised parts of the layer to be polished before conducting a polishing process using a harder polishing pad. Since the first polishing pad is flexible, porous and with low density, the first polishing pad can be deformed to increase contact areas between the first polishing pad and the raised part of the layer to be polished, and the abrasives are embedded easily in holes of the surface of the first polishing pad. Ultimately, the layer to be polished can be polished directly during the pre-polishing process. Therefore, the processing time is reduced, the consumption of the slurry is decreased and the process cost can be cut down substantially.
摘要翻译：描述了对具有待抛光层的基板进行化学机械抛光。在使用更硬的抛光垫进行抛光处理之前，使用较软的抛光垫进行预抛光工艺以去除待抛光层的部分凸起部分。由于第一抛光垫是柔性的，多孔的并且具有低密度，所以第一抛光垫可以变形以增加第一抛光垫与被抛光层的凸起部分之间的接触面积，并且磨料易于嵌入到第一抛光垫的表面。最终，抛光过程中可以直接抛光抛光层。因此，处理时间缩短，浆料的消耗量减少，工序成本大幅降低。

63. 发明授权

US5960279A Method of fabricating a capacitor on a rugged stacked oxide layer 失效
标题翻译：在坚固的堆叠氧化物层上制造电容器的方法
公开(公告)号：US5960279A
公开(公告)日：1999-09-28
申请号：US697622
申请日：1996-08-27
申请人： Kuang-Chao Chen , Tuby Tu
发明人： Kuang-Chao Chen , Tuby Tu
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/84
摘要： The present invention relates to a stacked memory capacitor of a DRAM cell, particularly, relates to a DRAM cell having a memory capacitor whose storage electrode possesses a remarkably increase area without increasing its occupation area and the complexity of fabrication thereof. By disposing the storage electrode of the memory capacitor on a rugged stacked oxide layer, the area of the storage electrode is remarkably enlarged since the growing of the storage electrode made of a doped polysilicon layer is followed along the topography of the rugged stacked oxide layer, thereby, resulting in a rugged surface thereof. The entire rugged surface of the storage electrode is covered with a dielectric layer to form a plate electrode made of a doped polysilicon layer. The memory capacitor provided by the invention achieves a higher capacitance while maintaining the same occupation area and packing density as that of the conventional arts.
摘要翻译：本发明涉及一种DRAM单元的堆叠式存储电容器，特别涉及一种具有存储电容器的存储电容器的DRAM单元，其存储电极具有显着增加的面积而不增加其占用面积及其制造的复杂性。通过将存储电容器的存储电极设置在坚固的堆叠氧化物层上，由于沿着凹凸的堆叠氧化物层的形貌遵循由掺杂多晶硅层制成的存储电极的生长，所以存储电极的面积显着增大，从而导致其表面粗糙。存储电极的整个粗糙表面被电介质层覆盖以形成由掺杂多晶硅层制成的平板电极。本发明提供的存储电容器在保持与传统技术相同的占用面积和封装密度的同时实现更高的电容。

64. 发明授权

US5883015A Method for using oxygen plasma treatment on a dielectric layer 失效
标题翻译：在电介质层上使用氧等离子体处理的方法
公开(公告)号：US5883015A
公开(公告)日：1999-03-16
申请号：US887886
申请日：1997-07-03
申请人： Kent Liao , Dinos Huang , Tuby Tu , Kuang-Chao Chen , Wen-Doe Su
发明人： Kent Liao , Dinos Huang , Tuby Tu , Kuang-Chao Chen , Wen-Doe Su
IPC分类号： C23C16/40 , H01L21/314 , H01L21/316
CPC分类号： H01L21/02164 , C23C16/402 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/0234 , H01L21/31612
摘要： The method for depositing a dielectric layer can be used to evenly deposit the dielectric layer to be applied to a semiconductor device. The method includes steps of: a) providing a substrate; b) depositing a first dielectric film on the subtrate; c) introducing an oxygen plasma for eliminating an uneven distribution of charges on a surface of the substrate; and d) forming a second dielectric film on the first dielectric film treated with the oxygen plasma for obtaining the dielectric layer having a uniform thickness on the substrate,
摘要翻译：用于沉积电介质层的方法可用于均匀地沉积要施加到半导体器件的介质层。该方法包括以下步骤：a）提供衬底; b）在所述缓冲液上沉积第一介电膜; c）引入氧等离子体以消除基板表面上电荷的不均匀分布; 以及d）在用氧等离子体处理的第一电介质膜上形成第二电介质膜，以获得在衬底上具有均匀厚度的电介质层，

65. 发明申请

US20160331966A1 HEARING AUXILIARY DEVICE AND HEARING AUXILIARY PROCESSING METHOD 审中-公开
标题翻译：听力辅助装置和听力辅助处理方法
公开(公告)号：US20160331966A1
公开(公告)日：2016-11-17
申请号：US15154547
申请日：2016-05-13
申请人： Kuang-Chao CHEN , Silicon Motion, Inc.
发明人： Kuang-Chao CHEN , Kuo-Liang YEH
IPC分类号： A61N1/36 , A61N1/05
CPC分类号： A61N1/36036 , A61N1/0541 , H04R25/606 , H04R25/70 , H04R2460/13
摘要： Disclosed is a hearing auxiliary device for helping a person with hearing impairment to obtain hearing information. The hearing auxiliary device includes a bone conduct transceiver, a receiver and a driver. The bone conduct transceiver converts a sound raw data to a bone conduct signal. The receiver is installed to an inner ear portion of the person with hearing impairment, and the receiver receives the bone conduct signal and converts the bone conduct signal to a sound restoration signal. The driver sends out a physical signal according to the sound restoration signal, in order to let the person with hearing impairment to obtain a hearing signal.
摘要翻译：公开了一种用于帮助听力障碍者获得听力信息的听力辅助装置。听力辅助装置包括骨传导收发器，接收器和驱动器。骨传导收发器将声音原始数据转换为骨传导信号。将接收器安装到具有听力障碍的人的内耳部，并且接收器接收骨传导信号并将骨传导信号转换成声音恢复信号。驾驶员根据声音恢复信号发出物理信号，以让听力障碍者获得听觉信号。

66. 发明申请

US20160206878A1 EXTERNAL ELECTRONIC EAR DEVICE AND COCHLEAR IMPLANT DEVICE 有权
标题翻译：外部电子耳设备和COCHLEAR IMPLANT DEVICE
公开(公告)号：US20160206878A1
公开(公告)日：2016-07-21
申请号：US14996239
申请日：2016-01-15
申请人： Kuang-Chao Chen , SILICON MOTION, INC.
发明人： Kuang-Chao Chen , Kuo-Liang Yeh
IPC分类号： A61N1/36 , A61N1/372 , A61N1/375 , A61N1/05
CPC分类号： A61N1/36032 , A61N1/0541 , A61N1/36036 , A61N1/37229 , A61N1/375
摘要： An external electronic ear device includes a housing, an external magnet, a microphone, a processing circuit and a wireless signal transmitter circuit. The external magnet is disposed in the housing and attracts a receiver magnet disposed under a scalp of a user. The microphone is disposed in the housing and receives an external sound and generates a sound signal corresponding to the external sound. The processing circuit is disposed in the housing and converts the sound signal into an electrode driving signal. The wireless signal transmitter circuit is disposed in the housing and transmits the electrode driving signal to a cochlear implant device in the cochlear system. The cochlear implant device converts the electrode driving signal into a plurality of electrode currents, and a plurality of electrical pulses are generated in a cochlear nerve of the user through a plurality of electrodes according to the electrode currents.
摘要翻译：外部电子耳机包括壳体，外部磁体，麦克风，处理电路和无线信号发射器电路。外部磁体设置在壳体中并吸引设置在使用者头皮下方的接收器磁体。麦克风设置在外壳中并接收外部声音，并产生对应于外部声音的声音信号。处理电路设置在壳体中并将声音信号转换成电极驱动信号。无线信号发射器电路设置在外壳中，并将电极驱动信号传输到耳蜗系统中的人工耳蜗植入装置。耳蜗植入装置将电极驱动信号转换为多个电极电流，并且根据电极电流通过多个电极在用户的耳蜗神经中产生多个电脉冲。

67. 发明授权

US09059094B2 Semiconductor gate structure and method of fabricating thereof 有权
标题翻译：半导体栅极结构及其制造方法
公开(公告)号：US09059094B2
公开(公告)日：2015-06-16
申请号：US13594100
申请日：2012-08-24
申请人： Chun Ling Chiang , Chun Ming Cheng , Kuang Chao Chen
发明人： Chun Ling Chiang , Chun Ming Cheng , Kuang Chao Chen
IPC分类号： H01L29/94 , H01L21/28 , H01L29/423
CPC分类号： H01L21/28167 , H01L21/28273 , H01L29/42324
摘要： A semiconductor gate structure is provided having a trench, the trench assembled by a dielectric structure and a stack structure. A first conductive layer may be conformally applied to the dielectric structure and the stack structure. An oxide layer is formed along the first conductive layer and may then be substantially removed from the first conductive layer. In certain gate structures, a conductive fill structure having the first conductive layer and a second conductive layer may be disposed on the stack structure and the dielectric structure.
摘要翻译：提供了具有沟槽的半导体栅极结构，沟槽由电介质结构和叠层结构组装。第一导电层可以共形地施加到电介质结构和堆叠结构。沿着第一导电层形成氧化物层，然后可以从第一导电层基本上除去。在某些栅极结构中，具有第一导电层和第二导电层的导电填充结构可以设置在堆叠结构和电介质结构上。

68. 发明授权

US08184288B2 Method of depositing a silicon-containing material by utilizing a multi-step fill-in process in a deposition machine 有权
标题翻译：通过在沉积机中利用多步填充工艺沉积含硅材料的方法
公开(公告)号：US08184288B2
公开(公告)日：2012-05-22
申请号：US12540001
申请日：2009-08-12
申请人： Tuung Luoh , Sheng-Hui Hsieh , Shing-Ann Luo , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
发明人： Tuung Luoh , Sheng-Hui Hsieh , Shing-Ann Luo , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
IPC分类号： G01J3/30
CPC分类号： H01J37/32972 , G01N21/68 , H01J37/32935
摘要： An advance process control (APC) system for a plasma process machine is provided, which includes at least an optical emission spectroscopy (OES) system and an APC analysis apparatus. The OES system is used for monitoring a testing object in the plasma process machine. The APC analysis apparatus is used for analyzing the data received from the OES system.
摘要翻译：提供了一种用于等离子体处理机的先进过程控制（APC）系统，其包括至少一个光发射光谱（OES）系统和APC分析装置。 OES系统用于监测等离子体处理机中的测试对象。 APC分析装置用于分析从OES系统接收到的数据。

69. 发明申请

US20120043657A1 METHOD FOR FABRICATING CONDUCTIVE LINES 有权
标题翻译：制导导线的方法
公开(公告)号：US20120043657A1
公开(公告)日：2012-02-23
申请号：US12860347
申请日：2010-08-20
申请人： Tuung Luoh , Ming Da Cheng , Chin-Ta Su , Tahone Yang , Kuang-Chao Chen
发明人： Tuung Luoh , Ming Da Cheng , Chin-Ta Su , Tahone Yang , Kuang-Chao Chen
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76885 , H01L21/76852 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating conductive metal lines of a semiconductor device are described herein. In one embodiment, such a method may comprise depositing a conductive material over a substrate, and depositing a first barrier layer on the conductive layer. Such a method may also comprise patterning a mask on the first barrier layer, the pattern comprising a layout of the conductive lines. Such an exemplary method may also comprise etching the conductive material and the first barrier layer using the patterned mask to form the conductive lines. In addition, a low temperature post-flow may be performed on the structure. The method may also include depositing a dielectric material over and between the patterned conductive lines.
摘要翻译：本文描述了制造半导体器件的导电金属线的方法。在一个实施例中，这种方法可以包括在衬底上沉积导电材料，以及在导电层上沉积第一阻挡层。这种方法还可以包括在第一阻挡层上图案化掩模，该图案包括导线的布局。这种示例性方法还可以包括使用图案化掩模蚀刻导电材料和第一阻挡层以形成导电线。此外，可以对结构进行低温后流。该方法还可以包括在图案化导电线之上和之间沉积电介质材料。

70. 发明授权

US08003519B2 Systems and methods for back end of line processing of semiconductor circuits 有权
标题翻译：半导体电路线路处理后端系统及方法
公开(公告)号：US08003519B2
公开(公告)日：2011-08-23
申请号：US11847135
申请日：2007-08-29
申请人： Tuung Luoh , Chi-Tung Huang , Kuang-Chao Chen , Candy Jiang
发明人： Tuung Luoh , Chi-Tung Huang , Kuang-Chao Chen , Candy Jiang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76864 , H01L21/76877
摘要： A BEOL manufacturing process for forming a via process between two metal lines on a semiconductor wafer comprises depositing a portion of a first metal adhesion layer within a patterned via hole, followed by a cooling step. The cooling step is then followed by formation of the remainder of the first metal adhesion layer and formation of a second metal adhesion layer within the patterned via hole. This process of forming the remaining portion of the first metal adhesion layer can be referred to as a wafer load, unload, load (LUL) process. By using a LUL process, thermal history is minimized, which reduces Al extrusion at the via interfaces.
摘要翻译：用于在半导体晶片上的两个金属线之间形成通孔工艺的BEOL制造工艺包括在图案化的通孔内沉积第一金属粘附层的一部分，接着进行冷却步骤。然后冷却步骤之后形成第一金属粘合层的其余部分，并在图案化的通孔内形成第二金属粘合层。形成第一金属粘合层的剩余部分的这个过程可以被称为晶片负载，卸载，负载（LUL）过程。通过使用LUL工艺，可以最大限度地减少热历史，从而减少通孔界面处的Al挤压。

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