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1. 发明申请

US20080099175A1 Method for in-gas micro/nanoimprinting of bulk metallic glass 审中-公开
标题翻译：散装金属玻璃的气体微/纳米压印方法
公开(公告)号：US20080099175A1
公开(公告)日：2008-05-01
申请号：US11790860
申请日：2007-04-27
申请人： Jinn P. Chu , Hadi Wijaya , Chun-Ling Chiang , Chih-Wei Wu
发明人： Jinn P. Chu , Hadi Wijaya , Chun-Ling Chiang , Chih-Wei Wu
IPC分类号： B22D25/02
CPC分类号： B22D17/2245 , B22D21/00 , C22C45/00
摘要： A method for in-gas micro/nanoimprinting of bulk metallic glass includes steps of preparing a die, heating the bulk metallic glass and in-gas micro/nanoimprinting of the bulk metallic glass. In the step of preparing a die, the die has a micro/nano structure having multiple depressions and a flow channel connected to the depressions. In the step of heating the bulk metallic glass, the bulk metallic glass is heated to a temperature between a glass transition temperature and a crystallization temperature of the bulk metallic glass. In the step of in-gas micro/nanoimprinting, the bulk metallic glass is forced into the die in presence of gas to imprint a complementing micro/nano structure on the bulk metallic glass. Because the die has a flow channel to allow air or gas to escape from the micro/nano structure of the die, the micro/nanoimprinting can be performed in presence of air or gas.
摘要翻译：本体金属玻璃的气体微/纳米压印的方法包括制备模具，加热块体金属玻璃和散装金属玻璃的气体微/纳米压印的步骤。在制备模具的步骤中，模头具有具有多个凹陷的微/纳米结构和与凹陷相连的流动通道。在加热块状金属玻璃的步骤中，将块状金属玻璃加热至玻璃化转变温度和块状金属玻璃的结晶温度之间的温度。在气体微/纳米压印的步骤中，在存在气体的情况下将大块金属玻璃强制进入模具，以在体金属玻璃上印刷互补的微/纳米结构。因为模具具有允许空气或气体从模具的微/纳米结构逸出的流动通道，所以微/纳米压印可以在存在空气或气体的情况下进行。

2. 发明申请

US20110175203A1 INTEGRATED CIRCUIT WITH IMPROVED INTRINSIC GETTERING ABILITY 失效
标题翻译：具有改进的内部获取能力的集成电路
公开(公告)号：US20110175203A1
公开(公告)日：2011-07-21
申请号：US13074780
申请日：2011-03-29
申请人： CHUN-LING CHIANG , JUNG-YU HSIEH , LING-WU YANG
发明人： CHUN-LING CHIANG , JUNG-YU HSIEH , LING-WU YANG
IPC分类号： H01L29/32
CPC分类号： H01L21/3225
摘要： An integrated circuit with improved intrinsic gettering ability is described, having a bulk micro-defect (BMD) density of 3.85×105-3.38×109/cm3 through first and second annealing steps. The first annealing step is performed at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. The second annealing step is performed at a second temperature higher than the first temperature in the atmosphere.
摘要翻译：描述了具有改善的内在吸气能力的集成电路，通过第一和第二退火步骤具有3.85×10 5 -3.38×10 9 / cm 3的体积微缺陷（BMD）密度。第一退火步骤在包含氧气和氮气中的至少一种的气氛中的第一温度下进行。第二退火步骤在高于大气中的第一温度的第二温度下进行。

3. 发明申请

US20100151657A1 METHOD OF IMPROVING INTRINSIC GETTERING ABILITY OF WAFER 有权
标题翻译：改善波浪的内在捕获能力的方法
公开(公告)号：US20100151657A1
公开(公告)日：2010-06-17
申请号：US12334829
申请日：2008-12-15
申请人： Chun-Ling Chiang , Jung-Yu Hsieh , Ling-Wu Yang
发明人： Chun-Ling Chiang , Jung-Yu Hsieh , Ling-Wu Yang
IPC分类号： H01L21/322
CPC分类号： H01L21/3225
摘要： A method of improving the intrinsic gettering ability of a wafer is described. A first annealing step is performed to the wafer at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. A second annealing step is performed to the wafer, at a second temperature higher than the first temperature, in the atmosphere.
摘要翻译：描述了提高晶片的固有吸气能力的方法。在包含氧气和氮气中的至少一种的气氛中的第一温度下对晶片进行第一退火步骤。在大气中在高于第一温度的第二温度下对晶片进行第二退火步骤。

4. 发明授权

US09059094B2 Semiconductor gate structure and method of fabricating thereof 有权
标题翻译：半导体栅极结构及其制造方法
公开(公告)号：US09059094B2
公开(公告)日：2015-06-16
申请号：US13594100
申请日：2012-08-24
申请人： Chun Ling Chiang , Chun Ming Cheng , Kuang Chao Chen
发明人： Chun Ling Chiang , Chun Ming Cheng , Kuang Chao Chen
IPC分类号： H01L29/94 , H01L21/28 , H01L29/423
CPC分类号： H01L21/28167 , H01L21/28273 , H01L29/42324
摘要： A semiconductor gate structure is provided having a trench, the trench assembled by a dielectric structure and a stack structure. A first conductive layer may be conformally applied to the dielectric structure and the stack structure. An oxide layer is formed along the first conductive layer and may then be substantially removed from the first conductive layer. In certain gate structures, a conductive fill structure having the first conductive layer and a second conductive layer may be disposed on the stack structure and the dielectric structure.
摘要翻译：提供了具有沟槽的半导体栅极结构，沟槽由电介质结构和叠层结构组装。第一导电层可以共形地施加到电介质结构和堆叠结构。沿着第一导电层形成氧化物层，然后可以从第一导电层基本上除去。在某些栅极结构中，具有第一导电层和第二导电层的导电填充结构可以设置在堆叠结构和电介质结构上。

5. 发明授权

US08106483B2 Wafer with improved intrinsic gettering ability 失效
标题翻译：晶圆具有改善的内在吸气能力
公开(公告)号：US08106483B2
公开(公告)日：2012-01-31
申请号：US13074780
申请日：2011-03-29
申请人： Chun-Ling Chiang , Jung-Yu Hsieh , Ling-Wu Yang
发明人： Chun-Ling Chiang , Jung-Yu Hsieh , Ling-Wu Yang
IPC分类号： H01L29/30 , H01L29/207 , H01L29/227 , H01L29/167
CPC分类号： H01L21/3225
摘要： An integrated circuit with improved intrinsic gettering ability is described, having a bulk micro-defect (BMD) density of 3.85×105-3.38×109/cm3 through first and second annealing steps. The first annealing step is performed at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. The second annealing step is performed at a second temperature higher than the first temperature in the atmosphere.
摘要翻译：描述了具有改善的内在吸气能力的集成电路，通过第一和第二退火步骤具有3.85×10 5 -3.38×10 9 / cm 3的体积微缺陷（BMD）密度。第一退火步骤在包含氧气和氮气中的至少一种的气氛中的第一温度下进行。第二退火步骤在高于大气中的第一温度的第二温度下进行。

6. 发明申请

US20140054655A1 SEMICONDUCTOR GATE STRUCTURE AND METHOD OF FABRICATING THEREOF 有权
标题翻译：半导体门结构及其制造方法
公开(公告)号：US20140054655A1
公开(公告)日：2014-02-27
申请号：US13594100
申请日：2012-08-24
申请人： Chun Ling Chiang , Chun Ming Cheng , Kuang Chao Chen
发明人： Chun Ling Chiang , Chun Ming Cheng , Kuang Chao Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28167 , H01L21/28273 , H01L29/42324
摘要： A semiconductor gate structure is provided having a trench, the trench assembled by a dielectric structure and a stack structure. A first conductive layer may be conformally applied to the dielectric structure and the stack structure. An oxide layer is formed along the first conductive layer and may then be substantially removed from the first conductive layer. In certain gate structures, a conductive fill structure having the first conductive layer and a second conductive layer may be disposed on the stack structure and the dielectric structure.
摘要翻译：提供了具有沟槽的半导体栅极结构，沟槽由电介质结构和叠层结构组装。第一导电层可以共形地施加到电介质结构和堆叠结构。沿着第一导电层形成氧化物层，然后可以从第一导电层基本上除去。在某些栅极结构中，具有第一导电层和第二导电层的导电填充结构可以设置在堆叠结构和电介质结构上。

7. 发明授权

US07939432B2 Method of improving intrinsic gettering ability of wafer 有权
标题翻译：提高晶片内在吸气能力的方法
公开(公告)号：US07939432B2
公开(公告)日：2011-05-10
申请号：US12334829
申请日：2008-12-15
申请人： Chun-Ling Chiang , Jung-Yu Hsieh , Ling-Wu Yang
发明人： Chun-Ling Chiang , Jung-Yu Hsieh , Ling-Wu Yang
IPC分类号： H01L21/322 , H01L21/335 , H01L21/8232
CPC分类号： H01L21/3225
摘要： A method of improving the intrinsic gettering ability of a wafer is described. A first annealing step is performed to the wafer at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. A second annealing step is performed to the wafer, at a second temperature higher than the first temperature, in the atmosphere.
摘要翻译：描述了提高晶片的固有吸气能力的方法。在包含氧气和氮气中的至少一种的气氛中的第一温度下对晶片进行第一退火步骤。在大气中在高于第一温度的第二温度下对晶片进行第二退火步骤。

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