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61. 发明授权

US5930592A Asymmetrical n-channel transistor having LDD implant only in the drain region 失效
标题翻译：具有LDD注入的非对称n沟道晶体管仅在漏极区中
公开(公告)号：US5930592A
公开(公告)日：1999-07-27
申请号：US720733
申请日：1996-10-01
申请人： Daniel Kadosh , Brad T. Moore , Jon D. Cheek
发明人： Daniel Kadosh , Brad T. Moore , Jon D. Cheek
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L21/265
CPC分类号： H01L21/28035 , H01L21/28176 , H01L29/4916 , H01L29/66659 , H01L29/7835 , H01L29/7836
摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.
摘要翻译：提供了用于产生p沟道和/或n沟道晶体管的各种工艺。因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。据此，本方法采用各种技术形成不对称晶体管。各种技术采用根据所需LDD结果而变化的处理步骤。首先，LDD注入只能在沟道的漏极侧，或在漏极侧以及源极侧进行。第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。可以存在许多其它修改和替代的处理步骤，其全部在此描述。不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

62. 发明授权

US5912188A Method of forming a contact hole in an interlevel dielectric layer using dual etch stops 失效
标题翻译：使用双蚀刻停止在层间电介质层中形成接触孔的方法
公开(公告)号：US5912188A
公开(公告)日：1999-06-15
申请号：US905686
申请日：1997-08-04
申请人： Mark I. Gardner , Daniel Kadosh , Frederick N. Hause
发明人： Mark I. Gardner , Daniel Kadosh , Frederick N. Hause
IPC分类号： H01L21/311 , H01L21/768 , H01L21/00
CPC分类号： H01L21/76832 , H01L21/31116 , H01L21/76802 , H01L21/76814 , H01L21/76834 , H01L21/76895
摘要： A method of forming a contact hole in an interlevel dielectric layer using dual etch stops includes the steps of providing a semiconductor substrate, forming a gate over the substrate, forming a source/drain region in the substrate, providing a source/drain contact electrically coupled to the source/drain region, forming an interlevel dielectric layer that includes first, second and third dielectric layers over the source/drain contact, forming an etch mask over the interlevel dielectric layer, applying a first etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop, thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer, applying a second etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop, thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact, and applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask, thereby forming a third hole in the third dielectric layer that extends to the source/drain contact, wherein the first, second and third holes in combination provide the contact hole. In this manner, the contact hole is formed in the interlevel dielectric without any appreciable gouging of the underlying materials.
摘要翻译：使用双蚀刻停止件在层间电介质层中形成接触孔的方法包括以下步骤：提供半导体衬底，在衬底上形成栅极，在衬底中形成源极/漏极区域，提供源/漏接触电耦合形成层间电介质层，该层间介质层包括在源极/漏极接触之上的第一，第二和第三电介质层，在层间电介质层上形成蚀刻掩模，施加第一蚀刻，第一蚀刻对第一电介质具有高选择性通过使用第二介电层作为蚀刻停止层，通过蚀刻掩模中的开口相对于第二介电层的层，从而在第一介电层中形成第一孔，该第一孔延伸到第二介电层而不延伸到第三介电层，施加相对于第三介电层通过开口而对第二电介质层具有高度选择性的第二蚀刻在蚀刻掩模中使用第三介电层作为蚀刻停止层，从而在第二介电层中形成延伸到第三介电层而不延伸到源极/漏极接触的第二孔，并施加高度选择性的第三蚀刻相对于通过蚀刻掩模中的开口的源极/漏极接触的第三电介质层，从而在延伸到源极/漏极接触的第三电介质层中形成第三孔，其中组合的第一，第二和第三孔提供接触孔。以这种方式，接触孔形成在层间电介质中，而没有任何明显的底层材料的气刨。

63. 发明授权

US5898189A Integrated circuit including an oxide-isolated localized substrate and a standard silicon substrate and fabrication method 失效
标题翻译：集成电路包括氧化物隔离的局部衬底和标准硅衬底及其制造方法
公开(公告)号：US5898189A
公开(公告)日：1999-04-27
申请号：US905614
申请日：1997-08-04
申请人： Mark I. Gardner , Daniel Kadosh , Michael Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael Duane
IPC分类号： H01L21/822 , H01L27/06 , H01L27/092 , H01L29/76 , H01L21/263 , H01L29/04
CPC分类号： H01L27/0922 , H01L21/8221 , H01L27/0688
摘要： A multi-dimensional transistor structure is fabricated which includes a base transistor substrate upon which transistors are formed. An elevated substrate is formed overlying the base transistor and having an oxide isolation formed in localized regions beneath the elevated substrate but overlying the base transistor substrate. A plurality of transistors are formed on a substrate wafer to form a base-level transistor formation. An intralevel dielectric (ILD) layer is deposited overlying the base-level transistor formation. Overlying the ILD layer, a "sandwich" structure is formed with the deposition of a first polysilicon layer, deposition of an oxide isolation layer, and deposition of a second polysilicon layer. The median oxide isolation layer is patterned and etched according to a localized oxide isolation mask in a configuration determined by the position of transistors in the base-level transistor formation and by the planned position of transistors, that are not yet formed, in an overlying elevated substrate level. The median oxide isolation layer is patterned and etched in a configuration so that isolation is achieved in a predetermined manner, for example, on an individual transistor basis, a transistor group basis, or the like. The resulting electronic integrated circuit structure is used for high speed circuit applications due to high packing densities and small distances between devices.
摘要翻译：制造了多维晶体管结构，其包括形成晶体管的基极晶体管基板。形成了一个升高的衬底，覆盖着基极晶体管，并且在升高的衬底下方的局部区域中形成氧化物隔离层，但覆盖在基极晶体管衬底上。在衬底晶片上形成多个晶体管，以形成基极晶体管结构。层叠电介质（ILD）层沉积在基极晶体管结构之上。覆盖ILD层，通过第一多晶硅层的沉积，氧化物隔离层的沉积和第二多晶硅层的沉积形成“三明治”结构。根据局部氧化物隔离掩模对中间氧化物隔离层进行构图和蚀刻，该隔离掩模的形状由基极晶体管形成中的晶体管的位置和尚未形成的晶体管的预定位置确定底物水平。对中间氧化物隔离层进行图案化和蚀刻，以使得以预定的方式实现隔离，例如基于单个晶体管，基于晶体管组等。所得的电子集成电路结构由于高封装密度和器件之间的距离小而用于高速电路应用。

64. 发明授权

US5885877A Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric 失效
标题翻译：复合栅电极，其与掺杂剂扩散阻滞层结合，邻近底层栅极电介质
公开(公告)号：US5885877A
公开(公告)日：1999-03-23
申请号：US837581
申请日：1997-04-21
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L29/49 , H01L21/336 , H01L21/3205
CPC分类号： H01L21/28035 , H01L29/4916
摘要： A composite gate electrode layer incorporates a diffusion-retarding barrier layer disposed at the bottom of the gate electrode layer to reduce the amount of dopant which diffuses into the gate dielectric layer from the gate electrode layer. A lower nitrogen-containing gate electrode layer provides a diffusion-retarding barrier layer against dopant diffusion into the gate dielectric layer disposed therebelow, and an upper gate electrode layer is formed upon the lower layer and is doped to form a highly conductive layer. Together the first and second gate electrode layers form a composite gate electrode layer which incorporates a diffusion-retarding barrier layer adjacent to the underlying gate dielectric layer. The barrier layer may be formed by annealing a first polysilicon layer in a nitrogen-containing ambient, such as N.sub.2, NO, N.sub.2 O, and NH.sub.3, by implanting a nitrogen-containing material, such as elemental or molecular nitrogen, into a first polysilicon layer, and by in-situ depositing a nitrogen-doped first polysilicon layer. Diffusion of dopants into the gate dielectric layer may be retarded, as most dopant atoms are prevented from diffusing from the composite gate electrode layer at all. In addition, the nitrogen concentration within the gate dielectric layer, particularly at or near the substrate interface, may be maintained at lower concentrations than otherwise necessary to prevent dopant diffusion into the underlying substrate. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness less than approximately 60 .ANG. when using a p-type dopant, such as boron.
摘要翻译：复合栅极电极层包括设置在栅极电极层底部的扩散阻挡层，以减少从栅极电极层扩散到栅极电介质层中的掺杂剂的量。下部含氮栅电极层提供阻止扩散阻挡层，以阻止掺杂剂扩散到设置在其下方的栅介质层中，并且在下层上形成上栅极电极层，并且被掺杂以形成高导电层。第一和第二栅极电极层一起形成复合栅极电极层，该复合栅极电极层包含与下面的栅极电介质层相邻的扩散阻滞阻挡层。通过将含氮材料（例如元素或分子氮）注入到第一多晶硅层中，可以通过在氮气环境如N 2，NO，N 2 O和NH 3中退火第一多晶硅层来形成阻挡层，并通过原位沉积氮掺杂的第一多晶硅层。完全可以防止掺杂剂扩散到栅极电介质层中，因为大多数掺杂剂原子被阻止从复合栅极电极层扩散。此外，栅极电介质层内，特别是在衬底界面处或附近的氮浓度可以保持在比防止掺杂剂扩散到下面的衬底中所必需的更低的浓度。本发明特别适用于薄栅电介质，例如当使用诸如硼的p型掺杂剂时厚度小于约60的薄电介质。

65. 发明授权

US5885761A Semiconductor device having an elevated active region formed from a thick polysilicon layer and method of manufacture thereof 失效
标题翻译：具有由厚多晶硅层形成的升高的有源区的半导体器件及其制造方法
公开(公告)号：US5885761A
公开(公告)日：1999-03-23
申请号：US780705
申请日：1997-01-08
申请人： Michael Duane , Daniel Kadosh , Mark I. Gardner
发明人： Michael Duane , Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L21/225 , H01L21/336 , H01L29/417 , H01L21/22 , H01L21/38 , H01L21/4763
CPC分类号： H01L29/66575 , H01L29/41775 , H01L29/41783 , H01L29/6659 , H01L21/2257 , H01L29/665
摘要： A semiconductor device and process for manufacture thereof is disclosed in which an elevated, active polysilicon region is formed by forming a gate electrode/nitride layer structure on a surface of a semiconductor substrate with spacers formed on adjacent walls to define an active region of the substrate. A thick polysilicon layer is formed over the resultant structure and then planarized leaving a portion of the polysilicon layer above the active region of the substrate. The remaining portion is doped to form an elevated active region.
摘要翻译：公开了一种半导体器件及其制造方法，其中通过在半导体衬底的表面上形成栅极/氮化物层结构形成升高的活性多晶硅区域，其中间隔物形成在相邻的壁上以限定衬底的有源区。在所得结构上形成厚的多晶硅层，然后平坦化，留下多晶硅层的一部分在衬底的有源区上方。剩余的部分被掺杂以形成升高的有源区。

66. 发明授权

US5863818A Multilevel transistor fabrication method having an inverted, upper level transistor 失效
标题翻译：具有反相上级晶体管的多电平晶体管制造方法
公开(公告)号：US5863818A
公开(公告)日：1999-01-26
申请号：US727050
申请日：1996-10-08
申请人： Daniel Kadosh , Mark I. Garnder , Robert Paiz
发明人： Daniel Kadosh , Mark I. Garnder , Robert Paiz
IPC分类号： H01L21/822 , H01L27/06 , H01L21/00
CPC分类号： H01L27/0688 , H01L21/8221
摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. In order to abut the gate conductors together, the upper level transistor is inverted relative to the lower level transistor. The inverted, upper level transistor thereby comprises a gate conductor residing in an elevation level below the gate dielectric and source/drain implants of that transistor. Direct coupling of one transistor gate conductor to another transistor gate conductor not only minimizes the overall routing between those conductors for the benefit of a high performance circuit, but also is particularly attuned to inverter circuits which utilize mutually connected gate conductors.
摘要翻译：提供了一种用于在半导体形貌的各种水平上产生有源和无源器件的工艺。因此，本方法可以实现三维装置的形成，以增强形成集成电路的总体密度。多级制造工艺不仅增加了整体电路密度，而且重点放在了在不同层次的器件之间的互连上。因此，引入了高性能互连，由此在一个晶体管级内的特征之间使互连尽可能短以达到另一晶体管级内的特征。互连通过在较低级晶体管的栅极导体上形成上层晶体管的栅极导体来实现较低的电阻率。为了将栅导体邻接在一起，上层晶体管相对于下层晶体管反相。反相的上级晶体管因此包括位于该晶体管的栅极电介质和源极/漏极注入下方的高度级的栅极导体。一个晶体管栅极导体与另一个晶体管栅极导体的直接耦合不仅使得这些导体之间的总体布线最小化，而且还有利于高性能电路，而且还特别适用于利用相互连接的栅极导体的逆变器电路。

67. 发明授权

US5841168A High performance asymmetrical MOSFET structure and method of making the same 失效
标题翻译：高性能非对称MOSFET结构及其制作方法
公开(公告)号：US5841168A
公开(公告)日：1998-11-24
申请号：US934509
申请日：1997-09-19
申请人： Mark I. Gardner , Fred Hause , Daniel Kadosh
发明人： Mark I. Gardner , Fred Hause , Daniel Kadosh
IPC分类号： H01L21/336 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66659 , H01L29/7835 , H01L29/6656 , Y10S257/90
摘要： A method of fabricating a high performance asymmetrical field effect transistor (FET)includes the steps of forming a gate oxide and a gate electrode on a layer of semiconductor material of a first conductivity type. The gate electrode includes a first side edge adjacent a first region of the semiconductor material and a second side edge proximate a second region of the semiconductor material. First and second lightly doped regions are formed in regions of the semiconductor material not covered by the gate oxide, and extending away from the first and second side edges of the gate electrode, respectively. First and second sidewall spacers are formed proximate the first and second side edges of the gate electrode, respectively, each sidewall spacer including a composite sidewall spacer of a first and a second spacer material. Lastly, a very highly doped source region and a highly doped drain region are formed in the first and second regions, respectively, the very highly doped source region having a greater dopant concentration of the second conductivity type than the highly doped drain region and the highly doped drain region having a dopant concentration greater than the lightly doped region extending away from the second side edge of said gate electrode. A novel FET is disclosed also.
摘要翻译：制造高性能不对称场效应晶体管（FET）的方法包括在第一导电类型的半导体材料层上形成栅极氧化物和栅电极的步骤。栅电极包括与半导体材料的第一区域相邻的第一侧边缘和靠近半导体材料的第二区域的第二侧边缘。第一和第二轻掺杂区域形成在半导体材料未被栅极氧化物覆盖的区域中，并且分别从栅电极的第一和第二侧边缘延伸。第一和第二侧壁间隔物分别形成在栅电极的第一和第二侧边缘附近，每个侧壁间隔物包括第一和第二间隔物材料的复合侧壁间隔物。最后，分别在第一和第二区域中形成非常高掺杂的源极区和高掺杂的漏极区，非常高掺杂的源极区具有比高掺杂漏极区高的掺杂浓度的第二导电类型，掺杂浓度的漏极区域的掺杂浓度大于远离所述栅电极的第二侧边缘延伸的轻掺杂区域。还公开了一种新颖的FET。

68. 发明授权

US5818069A Ultra high density series-connected transistors formed on separate elevational levels 失效
公开(公告)号：US5818069A
公开(公告)日：1998-10-06
申请号：US879509
申请日：1997-06-20
申请人： Daniel Kadosh , Mark I. Gardner
发明人： Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L27/06 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L27/0688
摘要： A three-dimensional integrated circuit and fabrication process is provided for producing active and passive devices on various levels of the integrated circuit. The present process is particularly suited to interconnecting a source of one transistor to a drain of another to form series-connected transistors often employed in core logic units. A junction of an underlying transistor can be connected to a junction of an overlying transistor, with both transistors separated by an interlevel dielectric. The lower transistor junction is connected to the upper level transistor junction using a plug conductor. The plug conductor and, more specifically, the mutually connected junction, is further coupled to a laterally extended interconnect. The interconnect extends from the mutual connection point of the plug conductor to a substrate of the overlying transistor. Accordingly, the source and substrate of the overlying transistor can be connected to a drain of the underlying transistor to not only achieve series-connection but also to connect the source and substrate of an internally configured transistor for the purpose of reducing body effects.

69. 发明授权

US5808319A Localized semiconductor substrate for multilevel transistors 失效
标题翻译：用于多层晶体管的局部半导体衬底
公开(公告)号：US5808319A
公开(公告)日：1998-09-15
申请号：US728601
申请日：1996-10-10
申请人： Mark I. Gardner , Daniel Kadosh
发明人： Mark I. Gardner , Daniel Kadosh
IPC分类号： H01L21/822 , H01L27/06 , H01L29/76 , H01L31/20 , H01L31/076
CPC分类号： H01L27/0688 , H01L21/8221
摘要： A dual level transistor integrated circuit and a fabrication technique for making the integrated circuit. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed upon a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate. The integrated circuit further includes a first transistor. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric. The integrated circuit further includes a first inter-substrate dielectric that is formed on the first conductive gate structure and the global substrate. A first local substrate is formed on an upper surface of the first inter-substrate dielectric. A second transistor is located within the first local substrate. The second transistor includes a second gate dielectric formed on an upper surface of the first local substrate and a second conductive gate structure formed on an upper surface of the second gate dielectric.
摘要翻译：一种双级晶体管集成电路和用于制造集成电路的制造技术。双电平晶体管是集成电路，其中第一晶体管形成在全局电介质的上表面上，并且第二晶体管形成在第一局部衬底的上表面上，使得第二晶体管垂直从第一晶体管。第一局部衬底形成在第一衬底间电介质上。通过垂直移位第一和第二晶体管，消除了在典型的单平面工艺中隔离第一和第二晶体管所需的横向分离。集成电路包括半导体全局基板。集成电路还包括第一晶体管。第一晶体管包括形成在全局衬底的上表面上的第一栅极电介质和形成在第一电介质的上表面上的第一导电栅极结构。集成电路还包括形成在第一导电栅极结构和全局基板上的第一基板间电介质。第一局部衬底形成在第一衬底间电介质的上表面上。第二晶体管位于第一局部衬底内。第二晶体管包括形成在第一局部衬底的上表面上的第二栅极电介质和形成在第二栅极电介质的上表面上的第二导电栅极结构。

70. 发明授权

US5780340A Method of forming trench transistor and isolation trench 失效
标题翻译：形成沟槽晶体管和隔离沟槽的方法
公开(公告)号：US5780340A
公开(公告)日：1998-07-14
申请号：US739566
申请日：1996-10-30
申请人： Mark I. Gardner , Daniel Kadosh , Jon D. Cheek
发明人： Mark I. Gardner , Daniel Kadosh , Jon D. Cheek
IPC分类号： H01L21/336 , H01L21/76 , H01L29/78
CPC分类号： H01L29/66583 , H01L21/76 , H01L29/66613 , H01L29/66621 , H01L29/7834
摘要： An IGFET with a gate electrode in a transistor trench adjacent to an isolation trench is disclosed. The trenches are formed in a semiconductor substrate. A gate insulator is on a bottom surface of the transistor trench, insulative spacers are adjacent to opposing sidewalls of the transistor trench, and the gate electrode is on the gate insulator and spacers and is electrically isolated from the substrate. Substantially all of the gate electrode is within the transistor trench. A source and drain in the substrate are beneath and adjacent to the bottom surface of the transistor trench. The isolation trench is filled with an insulator and provides device isolation for the IGFET. Advantageously, the trenches are formed simultaneously using a single etch step.
摘要翻译：公开了一种在与隔离沟槽相邻的晶体管沟槽中具有栅电极的IGFET。沟槽形成在半导体衬底中。栅极绝缘体位于晶体管沟槽的底表面上，绝缘间隔物与晶体管沟槽的相对的侧壁相邻，并且栅极电极位于栅极绝缘体和间隔物上，并与衬底电隔离。基本上所有的栅电极都在晶体管沟槽内。衬底中的源极和漏极在晶体管沟槽的底表面下方并且邻近晶体管沟槽的底表面。绝缘体填充绝缘体，并为IGFET提供器件隔离。有利地，使用单个蚀刻步骤同时形成沟槽。

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