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61. 发明授权

US06380571B1 CMOS compatible pixel cell that utilizes a gated diode to reset the cell 有权
标题翻译： CMOS兼容像素单元，利用门控二极管复位单元
公开(公告)号：US06380571B1
公开(公告)日：2002-04-30
申请号：US09173276
申请日：1998-10-14
申请人： Alexander Kalnitsky , Albert Bergemont , Pavel Poplevine
发明人： Alexander Kalnitsky , Albert Bergemont , Pavel Poplevine
IPC分类号： H01L31113
CPC分类号： H01L27/14654 , H01L27/14609 , H01L27/1463
摘要： The potential on a pixel cell having a gated diode and a read out transistor is set to an initial level prior to an image integration period. During the image integration period, absorbed photons cause the potential on the pixel cell to change. After the image integration period, the pixel cell is then reset and read out by applying a number of pulses to the gated diode. Each of the pulses causes a fixed amount of charge to be injected into the cell. When the potential on the cell has again returned to the initial level, the number of absorbed photons is determined by counting the number of pulses that were required to return the potential to the initial level. The read out transistor is used to determine when the potential is at the initial level by biasing the transistor to output a current that corresponds to the potential on the pixel cell.
摘要翻译：具有门控二极管和读出晶体管的像素单元上的电位在图像积分周期之前被设置为初始电平。在图像积分期间，吸收的光子导致像素单元的电位发生变化。在图像积分周期之后，通过向门控二极管施加多个脉冲来复位和读出像素单元。每个脉冲导致固定量的电荷注入到电池中。当电池上的电位再次恢复到初始电平时，通过计算将电位恢复到初始电平所需的脉冲数来确定吸收光子的数量。读出晶体管用于通过偏置晶体管来输出对应于像素单元上的电位的电流来确定电位何时处于初始电平。

62. 发明授权

US06300220B1 Process for fabricating isolation structure for IC featuring grown and buried field oxide 有权
标题翻译：用于制造具有生长和掩埋场氧化物的IC的隔离结构的方法
公开(公告)号：US06300220B1
公开(公告)日：2001-10-09
申请号：US09479316
申请日：2000-01-06
申请人： Albert Bergemont
发明人： Albert Bergemont
IPC分类号： H01L2176
CPC分类号： H01L29/66265 , H01L21/76264 , H01L21/76281 , H01L21/76283 , H01L29/7317
摘要： An isolation structure having both deep and shallow components is formed in a semiconductor workpiece by etching the workpiece to define raised precursor active device regions separated by sunken precursor isolation regions. An oxidation mask is formed to expose the precursor isolation regions, and the unmasked precursor isolation regions are exposed to oxidizing conditions to grow field oxides as the deep isolation component. Thermal growth of these field oxides creates topography which includes shallow recesses adjacent to the raised precursor active device regions. Deposition of conformal dielectric material such as high density plasma (HDP) deposited silicon oxide over the entire surface and within the recesses creates the shallow isolation component. Following planarization of the conformal dielectric material, fabrication of the device is completed by introducing conductivity-altering dopant into raised precursor active device regions. Vertical isolation of the device from the underlying material is provided by a subsurface dielectric or doped layer in contact with the deep isolation component.
摘要翻译：通过蚀刻工件在半导体工件中形成具有深度和浅部分的隔离结构，以限定由凹陷的前体隔离区隔开的凸起的前体活性器件区域。形成氧化掩模以暴露前体隔离区，并且将未掩蔽的前体隔离区暴露于氧化条件以生长作为深度隔离组分的场氧化物。这些场氧化物的热生长产生形貌，其包括与升高的前体活性器件区域相邻的浅凹槽。在整个表面和凹槽内沉积诸如高密度等离子体（HDP）沉积氧化硅的保形介质材料形成浅隔离部件。在保形电介质材料的平坦化之后，通过将导电性改变的掺杂剂引入凸起的前体有源器件区域来完成器件的制造。器件与下层材料的垂直隔离由与深度隔离部件接触的地下电介质或掺杂层提供。

63. 发明授权

US06277724B1 Method for forming an array of sidewall-contacted antifuses having diffused bit lines 有权
标题翻译：用于形成具有扩散位线的侧壁接触反熔丝阵列的方法
公开(公告)号：US06277724B1
公开(公告)日：2001-08-21
申请号：US09233370
申请日：1999-01-19
申请人： Albert Bergemont , Alexander Kalnitsky
发明人： Albert Bergemont , Alexander Kalnitsky
IPC分类号： H01L2144
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An array of sidewall-contacted antifuses is formed by a method that reduces the sensitivity of the array to masking alignment errors. The method forms a plurality of spaced-apart bit lines in a semiconductor material. Rows and columns of insulated contacts are formed on the semiconductor material such that each bit line is contacted a plurality of times by an insulated contact. In each row of contacts, each contact has an exposed sidewall. A plurality of word lines are then formed over the contacts such that a word line is formed over each exposed sidewall in a row of exposed sidewalls. The word lines include a dielectric layer and an overlying layer of conductive material.
摘要翻译：通过一种降低阵列对屏蔽对准误差的灵敏度的方法形成侧壁接触的反熔丝阵列。该方法在半导体材料中形成多个间隔开的位线。绝缘触点的行和列形成在半导体材料上，使得每个位线通过绝缘接触多次接触。在每排触点中，每个触点具有暴露的侧壁。然后在触点上形成多个字线，使得在一排暴露的侧壁中的每个暴露的侧壁上形成字线。字线包括电介质层和导电材料的上覆层。

64. 发明授权

US06262460B1 Long channel MOS transistor that utilizes a schottky diode to increase the threshold voltage of the transistor 有权
标题翻译：利用肖特基二极管来增加晶体管的阈值电压的长沟道MOS晶体管
公开(公告)号：US06262460B1
公开(公告)日：2001-07-17
申请号：US09480722
申请日：2000-01-07
申请人： Alexander Kalnitsky , Pavel Poplevine , Albert Bergemont
发明人： Alexander Kalnitsky , Pavel Poplevine , Albert Bergemont
IPC分类号： H01L2972
CPC分类号： H01L27/0629
摘要： When the threshold voltage of a long-channel transistor is set during the same dopant step of a manufacturing process that sets the threshold voltage of a short-channel transistor, the threshold voltage of the long-channel transistor is increased by connecting the long-channel transistor in series with a schottky diode.
摘要翻译：当在设定短沟道晶体管的阈值电压的制造过程的相同掺杂剂步骤期间设置长沟道晶体管的阈值电压时，通过连接长沟道晶体管的阈值电压来增加长沟道晶体管的阈值电压晶体管与肖特基二极管串联。

65. 发明授权

US06225163B1 Process for forming high quality gate silicon dioxide layers of multiple thicknesses 有权
标题翻译：用于形成多个厚度的高质量栅极二氧化硅层的工艺
公开(公告)号：US06225163B1
公开(公告)日：2001-05-01
申请号：US09507708
申请日：2000-02-18
申请人： Albert Bergemont
发明人： Albert Bergemont
IPC分类号： H01L2100
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/823462 , H01L21/823481 , Y10S438/981
摘要： A process for forming high quality gate silicon dioxide layers of multiple thicknesses. The process includes steps of first providing a semiconductor substrate (e.g., a silicon wafer) with at least a first active area, a second active area and an electrical isolation region separating the first and second active area, followed by the formation of a first gate silicon dioxide layer of a predetermined thickness (typically less than 100 angstroms) on the first and second active areas. A first silicon layer (e.g., a polysilicon or amorphous silicon layer) is then deposited on the first gate silicon dioxide layer and the electrical isolation region. Next, the first silicon layer is patterned using, for example, photolithographic and etching techniques, to form a patterned first silicon layer and to expose a portion of the first gate silicon dioxide layer that was grown on the second active area. Next, the exposed portion of the first gate silicon dioxide layer is removed and a second gate silicon dioxide layer of another predetermined thickness is formed on the second active area. A second silicon layer (e.g., a polysilicon or amorphous silicon layer) is then deposited on the second gate silicon dioxide layer and overlying the patterned first silicon layer. Finally, the second silicon layer is patterned to form a patterned second silicon layer.
摘要翻译：用于形成多个厚度的高质量栅极二氧化硅层的工艺。该方法包括以下步骤：首先提供具有至少第一有源区域，第二有源区域和分离第一和第二有源区域的电隔离区域的半导体衬底（例如，硅晶片），随后形成第一栅极在第一和第二有效区域上具有预定厚度（通常小于100埃）的二氧化硅层。然后将第一硅层（例如，多晶硅或非晶硅层）沉积在第一栅极二氧化硅层和电隔离区上。接下来，使用例如光刻和蚀刻技术对第一硅层进行图案化，以形成图案化的第一硅层并暴露在第二有源区上生长的第一栅极二氧化硅层的一部分。接下来，去除第一栅极二氧化硅层的暴露部分，并且在第二有源区域上形成另一预定厚度的第二栅极二氧化硅层。然后将第二硅层（例如，多晶硅或非晶硅层）沉积在第二栅极二氧化硅层上并覆盖图案化的第一硅层。最后，将第二硅层图案化以形成图案化的第二硅层。

66. 发明授权

US06184557B2 I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event and as diodes for ESD protection 有权
标题翻译：使用一对阱结构作为电阻延迟ESD事件的I / O电路和用于ESD保护的二极管
公开(公告)号：US06184557B2
公开(公告)日：2001-02-06
申请号：US09239344
申请日：1999-01-28
申请人： Pavel Poplevine , Alexander Kalnitsky , Hengyang (James) Lin , Albert Bergemont
发明人： Pavel Poplevine , Alexander Kalnitsky , Hengyang (James) Lin , Albert Bergemont
IPC分类号： H01L2362
CPC分类号： H01L27/0255 , H01L27/0288
摘要： The n-channel and p-channel driver transistors of an I/O circuit are electrostatic discharge (ESD) protected by utilizing a pair of well structures that resistively delay an ESD event from reaching the driver transistors, and that form diodes that direct the ESD event to the supply rail or ground of the circuit.
摘要翻译： I / O电路的n沟道和p沟道驱动器晶体管是通过利用一对阱电阻保护的静电放电（ESD），其阻止ESD事件到达驱动器晶体管，并且形成指示ESD的二极管事件到电路的电源轨或接地。

67. 发明授权

US06184552B2 Non-volatile memory cell with non-trenched substrate 失效
标题翻译：具有非沟槽衬底的非易失性存储单元
公开(公告)号：US06184552B2
公开(公告)日：2001-02-06
申请号：US09118574
申请日：1998-07-17
申请人： Alexander Kalnitsky , Albert Bergemont
发明人： Alexander Kalnitsky , Albert Bergemont
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/11524
摘要： In a non-volatile memory cell that has a select transistor and a memory transistor, the substrate trenching that occurs when the gate of the select transistor and the stacked gate of the memory transistor are initially defined is eliminated by forming the gate of the select transistor and the stacked gate of the memory transistor to have substantially the same step height.
摘要翻译：在具有选择晶体管和存储晶体管的非易失性存储单元中，通过形成选择晶体管的栅极来消除当选择晶体管的栅极和存储晶体管的堆叠栅极最初被限定时发生的衬底沟槽并且存储晶体管的堆叠栅极具有基本上相同的台阶高度。

68. 发明授权

US06180994B2 Array of sidewall-contacted antifuses having diffused bit lines 有权
标题翻译：具有扩散位线的侧壁接触反熔丝阵列
公开(公告)号：US06180994B2
公开(公告)日：2001-01-30
申请号：US09234007
申请日：1999-01-19
申请人： Albert Bergemont , Alexander Kalnitsky
发明人： Albert Bergemont , Alexander Kalnitsky
IPC分类号： H01L2900
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An array of sidewall-contacted antifuses is formed by a method that reduces the sensitivity of the array to masking alignment errors. The array includes a plurality of spaced-apart bit lines which are formed in a semiconductor material. Rows and columns of insulated contacts are formed on the semiconductor material such that each bit line is contacted a plurality of times by an insulated contact. In each row of contacts, each contact has an exposed sidewall. A plurality of word lines are formed over the contacts such that a word line is formed over each exposed sidewall in a row of exposed sidewalls. The word line includes a dielectric layer and a conductive layer.
摘要翻译：通过一种降低阵列对屏蔽对准误差的灵敏度的方法形成侧壁接触的反熔丝阵列。阵列包括形成在半导体材料中的多个间隔开的位线。绝缘触点的行和列形成在半导体材料上，使得每个位线通过绝缘接触多次接触。在每排触点中，每个触点具有暴露的侧壁。在触点上形成多个字线，使得在一排暴露的侧壁中的每个暴露的侧壁上形成字线。字线包括电介质层和导电层。

69. 发明授权

US6166421A Polysilicon fuse that provides an open current path when programmed without exposing the fuse to the environment 有权
标题翻译：多晶硅保险丝在编程时提供开路电流路径，而不会将保险丝暴露在环境中
公开(公告)号：US6166421A
公开(公告)日：2000-12-26
申请号：US376226
申请日：1999-08-18
申请人： Alexander Kalnitsky , Albert Bergemont
发明人： Alexander Kalnitsky , Albert Bergemont
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The contamination introduced into a conventional fuse via the window opening of the fuse is eliminated by forming a fuse with a cavity. When the fuse is programmed by passing a current through the fuse which is sufficient to heat up the fuse material, the heated fuse material flows up into the cavity, thereby providing an open current path.
摘要翻译：通过形成具有空腔的保险丝来消除通过保险丝的窗口引入常规保险丝的污染物。当熔断器通过使电流通过保险丝进行编程，该电流足以加热保险丝材料时，加热的熔丝材料向上流入空腔，从而提供开路电流路径。

70. 发明授权

US6157574A Erasable frohmann-bentchkowsky memory transistor that stores multiple bits of data 有权
标题翻译：可擦除的rubhmann-bentchkowsky存储晶体管存储多个数据位
公开(公告)号：US6157574A
公开(公告)日：2000-12-05
申请号：US394299
申请日：1999-09-10
申请人： Alexander Kalnitsky , Albert Bergemont
发明人： Alexander Kalnitsky , Albert Bergemont
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10 , G11C16/26 , H01L27/115 , H01L29/788
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0408 , G11C16/0433 , G11C16/10 , G11C16/26 , H01L27/115 , H01L27/11519 , H01L29/7887 , G11C2216/10 , G11C7/06
摘要： Multiple bits of data are stored in an erasable Frohmann-Bentchkowsky p-channel memory transistor which has a plurality of upper plates that are switchably connectable to an erase voltage. The multiple bits of data define a number of logic states which, in turn, define a number of corresponding charge ranges on the floating gate. The charge ranges include a first charge range and a plurality of remaining charge ranges. Each remaining charge range is associated with a different combination of upper plates. Electrons are injected onto the floating gate so that the charge on the floating gate falls within the first charge range. To place the charge within one of the remaining charge ranges, electrons are removed from the floating gate by connecting the upper plates that are associated with the desired charge range to the erase voltage to partially erase the transistor.
摘要翻译：多位数据存储在可擦除的Frohmann-Bentchkowsky p沟道存储晶体管中，该晶体管具有可切换地连接到擦除电压的多个上板。多个数据位定义了多个逻辑状态，这些逻辑状态又决定了浮动栅极上的相应电荷范围的数量。电荷范围包括第一电荷范围和多个剩余电荷范围。每个剩余电荷范围与上板的不同组合相关联。将电子注入到浮置栅极上，使得浮置栅极上的电荷落入第一充电范围内。为了将电荷置于剩余电荷范围之一内，通过将与期望电荷范围相关联的上板连接到擦除电压以将晶体管部分地擦除，从浮置栅极去除电子。

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