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61. 发明授权

US07272797B1 System and method for information transfer over a network 有权
标题翻译：通过网络进行信息传输的系统和方法
公开(公告)号：US07272797B1
公开(公告)日：2007-09-18
申请号：US09343758
申请日：1999-06-30
申请人： Dimitri Kanevsky , Clifford Alan Pickover , Wlodek Zadrozny , Alexander Zlatsin
发明人： Dimitri Kanevsky , Clifford Alan Pickover , Wlodek Zadrozny , Alexander Zlatsin
IPC分类号： G06F3/00
CPC分类号： G06F17/30905 , H04L67/42
摘要： An interface device for connecting to and retrieving data from a remote computer system, and method of compressing, decompressing and transferring data therefor. A user may set transfer constraints on the interface device. The interface device may be a web browser. The user selecting a web site requests data, normally image data from a remote computer system. The interface device includes a cache memory where generic objects may be stored. Each generic object corresponds to an original object in the requested data. Depending on the data transfer constraints, instead of retrieving the entire image, e.g., web page image, unaltered from the host system, a compact generic image is retrieved, initially, wherein generic objects are substituted for each corresponding original object. A pseudo-image is displayed, with the generic objects substituted for corresponding original objects. Subsequently received original objects may be substituted for generic objects as each original object is received.
摘要翻译：用于连接和从远程计算机系统检索数据的接口设备，以及压缩，解压缩和传送数据的方法。用户可以在接口设备上设置传输约束。接口设备可以是web浏览器。选择网站的用户请求数据，通常是来自远程计算机系统的图像数据。接口设备包括可以存储通用对象的高速缓冲存储器。每个通用对象对应于所请求数据中的原始对象。取决于数据传输约束，而不是从主机系统检索整个图像（例如，网页图像），而是从主机系统中检索出一个紧凑的通用图像，其中一般对象被代替每个对应的原始对象。显示伪图像，通用对象代替相应的原始对象。随后收到的原始对象可以替换为每个原始对象被接收的通用对象。

62. 发明授权

US07237217B2 Resonant tree driven clock distribution grid 失效
标题翻译：共振树驱动时钟分配网格
公开(公告)号：US07237217B2
公开(公告)日：2007-06-26
申请号：US10720564
申请日：2003-11-24
申请人： Phillip J. Restle
发明人： Phillip J. Restle
IPC分类号： G06F17/50
CPC分类号： G06F1/10
摘要： An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.
摘要翻译：用于在集成电路中分配时钟信号的集成电路（IC），IC组件和电路包括其中具有至少一个导体的电容时钟分配电路。在集成电路的金属层中形成至少一个电感器，并且耦合到时钟分配电路。通常以分布在整个集成电路中的多个螺旋电感器的形式的电感器提供选择为在谐振时与电容时钟分配电路谐振的电感值，降低功率消耗，同时可以提高歪斜和抖动性能。

63. 发明授权

US07219273B2 Method for testing media in a library without inserting media into the library database 有权
标题翻译：用于在库中测试介质而不将介质插入库数据库的方法
公开(公告)号：US07219273B2
公开(公告)日：2007-05-15
申请号：US10644209
申请日：2003-08-20
申请人： James Arthur Fisher , Anthony Andrew Lambert
发明人： James Arthur Fisher , Anthony Andrew Lambert
IPC分类号： G11C29/08 , G11C29/50
CPC分类号： G11B15/07 , G11B5/86 , G11B7/28 , G11B15/689 , G11B27/002 , G11B27/34 , G11B27/36 , G11B2220/41 , G11B2220/90
摘要： A storage subsystem, method of testing storage media in the storage subsystem and program product therefor. The storage media, e.g., magnetic tape in a physical volume, is inserted into an input area in the storage subsystem, but not loaded into the subsystem library. The media input area on the physical volume is scanned and a test command is queued. The test storage media is moved to a drive for testing. After testing, the storage media is returned to the input area.
摘要翻译：存储子系统，存储子系统中的存储介质测试方法及其程序产品。存储介质，例如物理卷中的磁带被插入到存储子系统中的输入区域中，但不被加载到子系统库中。扫描物理卷上的媒体输入区域，并将测试命令排队。将测试存储介质移动到驱动器进行测试。测试后，存储介质返回到输入区域。

64. 发明授权

US07120327B2 Backplane assembly with board to board optical interconnections 有权
标题翻译：背板组件，具有板对板光互连
公开(公告)号：US07120327B2
公开(公告)日：2006-10-10
申请号：US10305853
申请日：2002-11-27
申请人： Ferenc M. Bozso , Philip G. Emma
发明人： Ferenc M. Bozso , Philip G. Emma
IPC分类号： G02B6/26
CPC分类号： G06F13/409 , G02B6/43
摘要： An electronic system with components communicating over optical channels, a board initialization and continuity check and a method of transferring data over the optical channels. The system include a backplane with board to board signal wiring and a shared optical bus. Optical gratings are attached to the backplane and to circuit boards to pass optical energy between an optical transceiver and board/backplane. An optical transceiver at each end of each optical jumper relays optical signals between the optical jumpers and the connected circuit board or the backplane. Optical jumpers optically connect the circuit boards to the backplane.
摘要翻译：具有通过光信道通信的组件的电子系统，板初始化和连续性检查以及通过光信道传送数据的方法。该系统包括具有板对板信号布线和共享光学总线的背板。光栅连接到背板和电路板以在光收发器和板/背板之间传递光能。每个光学跳线的每端的光收发器在光学跳线和连接的电路板或背板之间中继光信号。光跳线将电路板光学连接到背板。

65. 发明授权

US07107121B2 Autonomic fiducial search pattern in an automated tape library 失效
标题翻译：自动化磁带库中的自动基准搜索模式
公开(公告)号：US07107121B2
公开(公告)日：2006-09-12
申请号：US10652439
申请日：2003-08-29
申请人： James Arthur Fisher , Nicholas James Pakidis , Kerri Renee Shotwell
发明人： James Arthur Fisher , Nicholas James Pakidis , Kerri Renee Shotwell
IPC分类号： G06F7/00
CPC分类号： G11B15/6835 , G11B17/225
摘要： A storage system or subsystem, method of locating components in the storage system and program product therefor. Storage system components have fiducial marks identifying component location. A sensor is located at an expected fiducial location and a first pass search for the fiducial is conducted along a search path. A second pass search, if needed, begins at a position located, horizontally, between the first pass start position and the system accessor home location.
摘要翻译：存储系统或子系统，定位组件在存储系统中的方法及其产品。存储系统组件具有标识组件位置的基准标记。传感器位于预期的基准位置，并且沿着搜索路径进行基准的第一遍搜索。如果需要，第二遍搜索从在第一遍起始位置和系统访问者归属位置之间的水平位置开始。

66. 发明授权

US07093206B2 Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures 失效
标题翻译：用于对片上互连结构进行建模和分析的计算机辅助设计方法和装置
公开(公告)号：US07093206B2
公开(公告)日：2006-08-15
申请号：US10690238
申请日：2003-10-21
申请人： Minakshisundaran B. Anand , Matthew S. Angyal , Alina Deutsch , Ibrahim M. Elfadel , Gerard V. Kopcsay , Barry J. Rubin , Howard H. Smith
发明人： Minakshisundaran B. Anand , Matthew S. Angyal , Alina Deutsch , Ibrahim M. Elfadel , Gerard V. Kopcsay , Barry J. Rubin , Howard H. Smith
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer aided design (CAD) system. A template generation engine generates templates from interconnect configuration files. A field solver generates high frequency passive element relationships from the templates. A circuit builder generates circuit description files from device technology models and from high frequency passive element relationships. Parameterized circuit description models may be generated for large range of sensitivity analyses. A simulator simulates circuit responses for transmission line models from the circuit description files. Interconnect configuration files may be generated by a geometry and material definition module that receives process description data from a designer.
摘要翻译：计算机辅助设计（CAD）系统。模板生成引擎从互连配置文件生成模板。场解算器从模板生成高频无源元件关系。电路构建器从器件技术模型和高频无源元件关系生成电路描述文件。可以为大范围的灵敏度分析生成参数化电路描述模型。模拟器模拟来自电路描述文件的传输线模型的电路响应。互连配置文件可以由接收来自设计者的过程描述数据的几何和材料定义模块生成。

67. 发明授权

US07089510B2 Method and program product of level converter optimization 失效
标题翻译：电平转换器优化的方法和程序产品
公开(公告)号：US07089510B2
公开(公告)日：2006-08-08
申请号：US10720562
申请日：2003-11-24
申请人： Anthony Correale, Jr. , David S. Kung , Douglass T. Lamb , Zhigang Pan , Ruchir Puri
发明人： Anthony Correale, Jr. , David S. Kung , Douglass T. Lamb , Zhigang Pan , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A method and program product for optimizing level converter placement in a multi supply integrated circuit. Each level converter is placed at a minimum power point to minimize net power and transitional delay from a first (low) voltage net source through the level converter and to a second (higher) voltage net sink. Then, inefficient level converters are eliminated. Level converters with fanin cones below a selected minimum cone size are deleted and low voltage sources to the deleted level converter reverted. Higher voltage level circuit elements receiving inputs from multiple level converters are replaced with equivalent low voltage circuit elements. Low voltage buffer driving level converters are both replaced by a single said level converter.
摘要翻译：一种用于优化多电源集成电路中的电平转换器放置的方法和程序产品。每个电平转换器被放置在最小功率点以最小化净功率和从第一（低）电压净源通过电平转换器到第二（较高）电压净接收器的过渡延迟。然后，消除了低效率的电平转换器。具有低于选定的最小锥度尺寸的扇形锥体的电平转换器被删除，并且删除的电平转换器的低电压源恢复。接收来自多电平转换器的输入的更高电压电平的电路元件被等效的低电压电路元件代替。低电压缓冲器驱动电平转换器都由单个所述电平转换器代替。

68. 发明授权

US07084476B2 Integrated circuit logic with self compensating block delays 有权
标题翻译：具有自补偿块延迟的集成电路逻辑
公开(公告)号：US07084476B2
公开(公告)日：2006-08-01
申请号：US10787488
申请日：2004-02-26
申请人： Puneet Gupta , Fook-Luen Heng , David S. Kung , Daniel L. Ostapko
发明人： Puneet Gupta , Fook-Luen Heng , David S. Kung , Daniel L. Ostapko
IPC分类号： H01L29/00
CPC分类号： H01L27/0207 , H01L27/092
摘要： An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.
摘要翻译：一种包括至少一个组合逻辑路径的集成电路（IC）。组合逻辑路径包括两种类型的逻辑块，其彼此补偿用于对单元晶体管的制造参数影响。这两种类型可以是在接触间距处具有场效应晶体管（FET）栅极的密集电池，并且具有FET栅极的隔离电池宽于接触间距。从被打印出焦点的FET栅极的密集单元延迟变化被隔离的单元延迟变化抵消。

69. 发明授权

US07076681B2 Processor with demand-driven clock throttling power reduction 失效
标题翻译：处理器采用需求驱动的时钟节流功率降低
公开(公告)号：US07076681B2
公开(公告)日：2006-07-11
申请号：US10187698
申请日：2002-07-02
申请人： Pradip Bose , Daniel M. Citron , Peter W. Cook , Philip G. Emma , Hans M. Jacobson , Prabhakar N. Kudva , Stanley E. Schuster , Jude A. Rivers , Victor V. Zyuban
发明人： Pradip Bose , Daniel M. Citron , Peter W. Cook , Philip G. Emma , Hans M. Jacobson , Prabhakar N. Kudva , Stanley E. Schuster , Jude A. Rivers , Victor V. Zyuban
IPC分类号： G06F1/04
CPC分类号： G06F9/3869 , G06F1/04 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F9/30083 , G06F9/3802 , G06F9/3836 , G06F9/384 , G06F9/3867 , Y02D10/126 , Y02D10/128 , Y02D10/152 , Y02D10/171
摘要： A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.
摘要翻译：同步集成电路，如标量处理器或超标量处理器。电路组件或单元由公共系统时钟计时并同步。至少两个时钟单元包括多个寄存器级，例如流水线级。每个时钟单元中的本地时钟发生器将来自一个或多个其他单元的公共系统时钟和失速状态相结合，以调整寄存器时钟频率向上或向下。

70. 发明授权

US07057923B2 Field emission phase change diode memory 失效
标题翻译：场发射相变二极管存储器
公开(公告)号：US07057923B2
公开(公告)日：2006-06-06
申请号：US10732582
申请日：2003-12-10
申请人： Stephen S. Furkay , David V. Horak , Chung H. Lam , Hon-Sum P. Wong
发明人： Stephen S. Furkay , David V. Horak , Chung H. Lam , Hon-Sum P. Wong
IPC分类号： G11C11/00 , H01L27/00 , H01L21/00
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： A storage cell that may be a memory cell, and integrated circuit (IC) chip including an array of the memory cells and a method of forming the IC. Each storage cell is formed between a top an bottom electrode. Each cell includes a phase change layer that may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) or GST layer. The cell also includes a stylus with the apex of the stylus contacting the GST layer. The apex may penetrate the GST layer
摘要翻译：可以是存储单元的存储单元和包括存储单元的阵列的集成电路（IC）芯片和形成IC的方法。每个存储单元形成在顶部底部电极之间。每个电池包括可以是硫族化物，特别是锗（Ge），锑（Sb），碲（Te）或GST层的相变层。电池还包括一个触笔，触笔的顶点与GST层接触。顶点可以穿透GST层

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