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1. 发明授权

US07089510B2 Method and program product of level converter optimization 失效
标题翻译：电平转换器优化的方法和程序产品
公开(公告)号：US07089510B2
公开(公告)日：2006-08-08
申请号：US10720562
申请日：2003-11-24
申请人： Anthony Correale, Jr. , David S. Kung , Douglass T. Lamb , Zhigang Pan , Ruchir Puri
发明人： Anthony Correale, Jr. , David S. Kung , Douglass T. Lamb , Zhigang Pan , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A method and program product for optimizing level converter placement in a multi supply integrated circuit. Each level converter is placed at a minimum power point to minimize net power and transitional delay from a first (low) voltage net source through the level converter and to a second (higher) voltage net sink. Then, inefficient level converters are eliminated. Level converters with fanin cones below a selected minimum cone size are deleted and low voltage sources to the deleted level converter reverted. Higher voltage level circuit elements receiving inputs from multiple level converters are replaced with equivalent low voltage circuit elements. Low voltage buffer driving level converters are both replaced by a single said level converter.
摘要翻译：一种用于优化多电源集成电路中的电平转换器放置的方法和程序产品。每个电平转换器被放置在最小功率点以最小化净功率和从第一（低）电压净源通过电平转换器到第二（较高）电压净接收器的过渡延迟。然后，消除了低效率的电平转换器。具有低于选定的最小锥度尺寸的扇形锥体的电平转换器被删除，并且删除的电平转换器的低电压源恢复。接收来自多电平转换器的输入的更高电压电平的电路元件被等效的低电压电路元件代替。低电压缓冲器驱动电平转换器都由单个所述电平转换器代替。

2. 发明申请

US20090032903A1 MULTIPLE VOLTAGE INTEGRATED CIRCUIT AND DESIGN METHOD THEREFOR 审中-公开
标题翻译：多电压集成电路及其设计方法
公开(公告)号：US20090032903A1
公开(公告)日：2009-02-05
申请号：US12251195
申请日：2008-10-14
申请人： Anthony Correale, JR. , David S. Kung , Douglass T. Lamb , Zhigang Pan , Ruchir Puri , David Wallach
发明人： Anthony Correale, JR. , David S. Kung , Douglass T. Lamb , Zhigang Pan , Ruchir Puri , David Wallach
IPC分类号： H01L29/00
CPC分类号： G06F17/5045 , G06F17/5068 , G06F2217/78 , H01L27/118
摘要： An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.
摘要翻译：一种用于降低IC设计功耗的集成电路（IC）设计，方法和程序产品。 IC以电路行组织。电路行可以包括由低电压（Vdd1）电源供电的低压岛和由高电压（Vddh）电源供电的高压岛。包括电池，锁存器和宏的电路元件放置有高电压或低电压岛，以尽量减少IC功率，同时保持整体性能。电平转换器可以放置高压电路元件。

3. 发明授权

US07480883B2 Multiple voltage integrated circuit and design method therefor 有权
标题翻译：多电压集成电路及其设计方法
公开(公告)号：US07480883B2
公开(公告)日：2009-01-20
申请号：US11460537
申请日：2006-07-27
申请人： Anthony Correale, Jr. , David S. Kung , Douglass T. Lamb , Zhigang Pan , Ruchir Puri , David Wallach
发明人： Anthony Correale, Jr. , David S. Kung , Douglass T. Lamb , Zhigang Pan , Ruchir Puri , David Wallach
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068 , G06F2217/78 , H01L27/118
摘要： An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.
摘要翻译：一种用于降低IC设计功耗的集成电路（IC）设计，方法和程序产品。 IC以电路行组织。电路行可以包括由低电压（Vdd1）电源供电的低压岛和由高电压（Vddh）电源供电的高压岛。包括电池，锁存器和宏的电路元件放置有高电压或低电压岛，以尽量减少IC功率，同时保持整体性能。电平转换器可以放置高压电路元件。

4. 发明授权

US07111266B2 Multiple voltage integrated circuit and design method therefor 有权
标题翻译：多电压集成电路及其设计方法
公开(公告)号：US07111266B2
公开(公告)日：2006-09-19
申请号：US10720464
申请日：2003-11-24
申请人： Anthony Correale, Jr. , David S. Kung , Douglass T. Lamb , Zhigang Pan , Ruchir Puri , David Wallach
发明人： Anthony Correale, Jr. , David S. Kung , Douglass T. Lamb , Zhigang Pan , Ruchir Puri , David Wallach
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068 , G06F2217/78 , H01L27/118
摘要： An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.
摘要翻译：一种用于降低IC设计功耗的集成电路（IC）设计，方法和程序产品。 IC以电路行组织。电路行可以包括由低电压（Vdd）电源供电的低压岛和由高电压（Vdd）供电供电的高电压岛。包括电池，锁存器和宏的电路元件放置有高电压或低电压岛，以尽量减少IC功率，同时保持整体性能。电平转换器可以放置高压电路元件。

5. 发明授权

US08188516B2 Creating integrated circuit capacitance from gate array structures 失效
标题翻译：从门阵列结构创建集成电路电容
公开(公告)号：US08188516B2
公开(公告)日：2012-05-29
申请号：US12717605
申请日：2010-03-04
申请人： Anthony Correale, Jr. , Benjamin J. Bowers , Douglass T. Lamb , Nishith Rohatgi
发明人： Anthony Correale, Jr. , Benjamin J. Bowers , Douglass T. Lamb , Nishith Rohatgi
IPC分类号： H01L27/10 , H01L23/52
CPC分类号： H01L27/11807 , H01L27/0207 , H01L27/11898 , H01L28/40
摘要： Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
摘要翻译：公开了在集成电路内使用门阵列来形成电容结构的技术。实施例包括将P型场效应晶体管（P-fets）和N型场效应晶体管（N-fets）的栅极阵列放置在集成电路设计中，将用于一个或多个P-fets和栅极的漏极和源耦合将一个或多个N-fets连接到电源地，以及将一个或多个P-fets的栅极和用于一个或多个N-fets的漏极和源耦合到电源的正电压。在一些实施例中，通过将一个或多个P-fets和一个或多个N-fets分别偏置到正电压和地电位，P-fets和N-fets的电容式设备的源极到漏极泄漏电流被最小化。在其他实施例中，可以使用可熔元件实现电容结构，以在短路的情况下隔离电容结构。

6. 发明授权

US07728362B2 Creating integrated circuit capacitance from gate array structures 失效
标题翻译：从门阵列结构创建集成电路电容
公开(公告)号：US07728362B2
公开(公告)日：2010-06-01
申请号：US11337010
申请日：2006-01-20
申请人： Anthony Correale, Jr. , Benjamin J. Bowers , Douglass T. Lamb , Nishith Rohatgi
发明人： Anthony Correale, Jr. , Benjamin J. Bowers , Douglass T. Lamb , Nishith Rohatgi
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , H01L27/0207 , H01L27/11898 , H01L28/40
摘要： Using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise having a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
摘要翻译：公开了使用门阵列来在集成电路内形成电容结构。实施例包括在集成电路设计中具有P型场效应晶体管（P-fets）和N型场效应晶体管（N-fets）的栅极阵列，将用于一个或多个P-fets和栅极的漏极和源耦合将一个或多个N-fets连接到电源地，以及将一个或多个P-fets的栅极和用于一个或多个N-fets的漏极和源耦合到电源的正电压。在一些实施例中，通过将一个或多个P-fets和一个或多个N-fets分别偏置到正电压和地电位，P-fets和N-fets的电容式设备的源极到漏极泄漏电流被最小化。在其他实施例中，可以使用可熔元件实现电容结构，以在短路的情况下隔离电容结构。

7. 发明申请

US20120190165A1 Creating Integrated Circuit Capacitance From Gate Array Structures 失效
标题翻译：从门阵列结构创建集成电路电容
公开(公告)号：US20120190165A1
公开(公告)日：2012-07-26
申请号：US13436993
申请日：2012-04-01
申请人： Anthony Correale, JR. , Benjamin J. Bowers , Douglass T. Lamb , Nishith Rohatgi
发明人： Anthony Correale, JR. , Benjamin J. Bowers , Douglass T. Lamb , Nishith Rohatgi
IPC分类号： H01L21/02
CPC分类号： H01L27/11807 , H01L27/0207 , H01L27/11898 , H01L28/40
摘要： Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
摘要翻译：公开了在集成电路内使用门阵列来形成电容结构的技术。实施例包括将P型场效应晶体管（P-fets）和N型场效应晶体管（N-fets）的栅极阵列放置在集成电路设计中，将用于一个或多个P-fets和栅极的漏极和源耦合将一个或多个N-fets连接到电源地，以及将一个或多个P-fets的栅极和用于一个或多个N-fets的漏极和源耦合到电源的正电压。在一些实施例中，通过将一个或多个P-fets和一个或多个N-fets分别偏置到正电压和地电位，P-fets和N-fets的电容式设备的源极到漏极泄漏电流被最小化。在其他实施例中，可以使用可熔元件实现电容结构，以在短路的情况下隔离电容结构。

8. 发明申请

US20100155800A1 Creating Integrated Circuit Capacitance from Gate Array Structures 失效
标题翻译：从门阵列结构创建集成电路电容
公开(公告)号：US20100155800A1
公开(公告)日：2010-06-24
申请号：US12717605
申请日：2010-03-04
申请人： Anthony Correale, JR. , Benjamin J. Bowers , Douglass T. Lamb , Nishith Rohatgi
发明人： Anthony Correale, JR. , Benjamin J. Bowers , Douglass T. Lamb , Nishith Rohatgi
IPC分类号： H01L27/06 , H01L21/768
CPC分类号： H01L27/11807 , H01L27/0207 , H01L27/11898 , H01L28/40
摘要： Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
摘要翻译：公开了在集成电路内使用门阵列来形成电容结构的技术。实施例包括将P型场效应晶体管（P-fets）和N型场效应晶体管（N-fets）的栅极阵列放置在集成电路设计中，将用于一个或多个P-fets和栅极的漏极和源耦合将一个或多个N-fets连接到电源地，以及将一个或多个P-fets的栅极和用于一个或多个N-fets的漏极和源耦合到电源的正电压。在一些实施例中，通过将一个或多个P-fets和一个或多个N-fets分别偏置到正电压和地电位，P-fets和N-fets的电容式设备的源极到漏极泄漏电流被最小化。在其他实施例中，可以使用可熔元件实现电容结构，以在短路的情况下隔离电容结构。

9. 发明授权

US08298888B2 Creating integrated circuit capacitance from gate array structures 失效
公开(公告)号：US08298888B2
公开(公告)日：2012-10-30
申请号：US13436993
申请日：2012-04-01
申请人： Anthony Correale, Jr. , Benjamin J. Bowers , Douglass T. Lamb , Nishith Rohatgi
发明人： Anthony Correale, Jr. , Benjamin J. Bowers , Douglass T. Lamb , Nishith Rohatgi
IPC分类号： H01L21/336
CPC分类号： H01L27/11807 , H01L27/0207 , H01L27/11898 , H01L28/40
摘要： Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.

10. 发明申请

US20110072407A1 Automatic Positioning of Gate Array Circuits in an Integrated Circuit Design 有权
标题翻译：门阵列电路在集成电路设计中的自动定位
公开(公告)号：US20110072407A1
公开(公告)日：2011-03-24
申请号：US12563021
申请日：2009-09-18
申请人： Joachim Keinert , Douglass T. Lamb , David W. Lewis , Shyam Ramji
发明人： Joachim Keinert , Douglass T. Lamb , David W. Lewis , Shyam Ramji
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An automated method and apparatus for positioning gate array circuits in an integrated circuit design. An initial integrated circuit design includes logic cells and gate array fill circuits positioned thereon. The gate array fill circuits are positioned in available space between the adjacent logic cells so as to fill the available space with the maximum gate array fill circuits. A gate array logic element to be positioned in the integrated circuit design, such as may be required by an engineering change to the circuit design, is automatically positioned between adjacent logic cells so as to allow for full utilization of any space remaining between the adjacent logic cells by gate array fill circuits.
摘要翻译：一种用于在集成电路设计中定位门阵列电路的自动化方法和装置。初始集成电路设计包括位于其上的逻辑单元和门阵列填充电路。门阵列填充电路位于相邻逻辑单元之间的可用空间中，以便用最大门阵列填充电路填充可用空间。位于集成电路设计中的门阵列逻辑元件（例如可能需要通过电路设计的工程改变）被自动地定位在相邻逻辑单元之间，以便允许充分利用相邻逻辑之间剩余的任何空间电池通过门阵列填充电路。

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