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1. 发明授权

US07084476B2 Integrated circuit logic with self compensating block delays 有权
标题翻译：具有自补偿块延迟的集成电路逻辑
公开(公告)号：US07084476B2
公开(公告)日：2006-08-01
申请号：US10787488
申请日：2004-02-26
申请人： Puneet Gupta , Fook-Luen Heng , David S. Kung , Daniel L. Ostapko
发明人： Puneet Gupta , Fook-Luen Heng , David S. Kung , Daniel L. Ostapko
IPC分类号： H01L29/00
CPC分类号： H01L27/0207 , H01L27/092
摘要： An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.
摘要翻译：一种包括至少一个组合逻辑路径的集成电路（IC）。组合逻辑路径包括两种类型的逻辑块，其彼此补偿用于对单元晶体管的制造参数影响。这两种类型可以是在接触间距处具有场效应晶体管（FET）栅极的密集电池，并且具有FET栅极的隔离电池宽于接触间距。从被打印出焦点的FET栅极的密集单元延迟变化被隔离的单元延迟变化抵消。

2. 发明授权

US07353492B2 Method of IC fabrication, IC mask fabrication and program product therefor 失效
标题翻译： IC制造方法，IC掩模制造及其程序产品
公开(公告)号：US07353492B2
公开(公告)日：2008-04-01
申请号：US11043482
申请日：2005-01-26
申请人： Puneet Gupta , Fook-Luen Heng , Mark A. Lavin
发明人： Puneet Gupta , Fook-Luen Heng , Mark A. Lavin
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method of forming integrated circuit (IC) chip shapes and a method and computer program product for converting an IC design to a mask, e.g., for standard cell design. Individual book/macro physical designs (layouts) are proximity corrected before unnesting and an outer proximity range is determined for each proximity corrected physical design. Shapes with a unique design (e.g., in boundary cells and unique instances of books) are tagged and the design is unnested. Only the unique shapes are proximity corrected in the unnested design, which may be used to make a mask for fabricating IC chips/wafers.
摘要翻译：一种形成集成电路（IC）芯片形状的方法以及用于将IC设计转换为掩模的方法和计算机程序产品，例如用于标准单元设计。单独的书/宏物理设计（布局）在不需要之前进行邻近校正，并且为每个邻近校正的物理设计确定外部接近度范围。具有独特设计的形状（例如，在边界单元格和图书的独特实例中）被标记，并且设计不被忽视。只有独特的形状在未设计的设计中被接近校正，其可以用于制造用于制造IC芯片/晶片的掩模。

3. 发明申请

US20050193363A1 Method of IC fabrication, IC mask fabrication and program product therefor 失效
标题翻译： IC制造方法，IC掩模制造及其程序产品
公开(公告)号：US20050193363A1
公开(公告)日：2005-09-01
申请号：US11043482
申请日：2005-01-26
申请人： Puneet Gupta , Fook-Luen Heng , Mark Lavin
发明人： Puneet Gupta , Fook-Luen Heng , Mark Lavin
IPC分类号： G03F1/14 , G06F17/50
CPC分类号： G03F1/36
摘要： A method of forming integrated circuit (IC) chip shapes and a method and computer program product for converting an IC design to a mask, e.g., for standard cell design. Individual book/macro physical designs (layouts) are proximity corrected before unnesting and an outer proximity range is determined for each proximity corrected physical design. Shapes with a unique design (e.g., in boundary cells and unique instances of books) are tagged and the design is unnested. Only the unique shapes are proximity corrected in the unnested design, which may be used to make a mask for fabricating IC chips/wafers.
摘要翻译：一种形成集成电路（IC）芯片形状的方法以及用于将IC设计转换为掩模的方法和计算机程序产品，例如用于标准单元设计。单独的书/宏物理设计（布局）在不需要之前进行邻近校正，并且为每个邻近校正的物理设计确定外部接近度范围。具有独特设计的形状（例如，在边界单元格和图书的独特实例中）被标记，并且设计不被忽视。只有独特的形状在未设计的设计中被接近校正，其可以用于制造用于制造IC芯片/晶片的掩模。

4. 发明申请

US20050189604A1 Integrated circuit logic with self compensating block delays 有权
标题翻译：具有自补偿块延迟的集成电路逻辑
公开(公告)号：US20050189604A1
公开(公告)日：2005-09-01
申请号：US10787488
申请日：2004-02-26
申请人： Puneet Gupta , Fook-Luen Heng , David Kung , Daniel Ostapko
发明人： Puneet Gupta , Fook-Luen Heng , David Kung , Daniel Ostapko
IPC分类号： H01L27/118 , G06F17/50 , H01L21/82 , H01L27/02 , H01L27/092 , H01L29/00 , H03K5/13
CPC分类号： H01L27/0207 , H01L27/092
摘要： An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.
摘要翻译：一种包括至少一个组合逻辑路径的集成电路（IC）。组合逻辑路径包括两种类型的逻辑块，其彼此补偿用于对单元晶体管的制造参数影响。这两种类型可以是在接触间距处具有场效应晶体管（FET）栅极的密集电池，并且具有FET栅极的隔离电池宽于接触间距。从被打印出焦点的FET栅极的密集单元延迟变化被隔离的单元延迟变化抵消。

5. 发明授权

US09210538B2 Method, system, and computer-readable medium for providing location-based listing services 有权
标题翻译：用于提供基于位置的列表服务的方法，系统和计算机可读介质
公开(公告)号：US09210538B2
公开(公告)日：2015-12-08
申请号：US13425849
申请日：2012-03-21
申请人： Puneet Gupta , Akshay Darbari , Venkat Kumar Sivaramamurthy
发明人： Puneet Gupta , Akshay Darbari , Venkat Kumar Sivaramamurthy
IPC分类号： H04W24/00 , H04W4/02 , H04W4/00 , H04W64/00
CPC分类号： H04W4/02 , H04W4/50 , H04W64/00
摘要： The present invention relates to a computer-implemented method, system and computer readable medium for providing context-based listing services. The method comprises registering at least one first service provider with an second service provider wherein registering comprises that the first service provider provides the information via a communication network to the second service provider and it validates the information. Validating comprises identify the location of the first service provider and/or request to at least one predefined user located nearby the location of the first service provider. At least one user requests the second service provider for the information via the communication network. At least one user retrieves the information and provides ranking to category of services so as to update the information in the second service provider.
摘要翻译：本发明涉及一种用于提供基于上下文的列表服务的计算机实现的方法，系统和计算机可读介质。该方法包括向第二服务提供商注册至少一个第一服务提供商，其中注册包括第一服务提供商经由通信网络向第二服务提供商提供信息，并验证该信息。验证包括将位于第一服务提供商的位置附近的至少一个预定义用户识别第一服务提供商的位置和/或请求。至少一个用户通过通信网络请求第二服务提供商的信息。至少一个用户检索信息并提供对服务类别的排名，以便更新第二服务提供商中的信息。

6. 发明授权

US09064538B2 Method and system for generating at least one of: comic strips and storyboards from videos 有权
标题翻译：用于从视频中生成漫画和故事板中的至少一个的方法和系统
公开(公告)号：US09064538B2
公开(公告)日：2015-06-23
申请号：US13311795
申请日：2011-12-06
申请人： Puneet Gupta , Akshay Darbari , Karthik Gopalakrishnan Vinmani , Venkat Kumar Sivaramamurthy
发明人： Puneet Gupta , Akshay Darbari , Karthik Gopalakrishnan Vinmani , Venkat Kumar Sivaramamurthy
IPC分类号： H04N5/93 , G11B27/034 , G11B27/10 , G11B27/28 , G11B27/34
CPC分类号： G11B27/034 , G11B27/105 , G11B27/28 , G11B27/34
摘要： A method, a system, and a computer program product code for generating a series of still images from an input video file are provided. The series of still images may include, but are not limited to, a comic strip and a storyboard. The method includes extracting audio and visual frames from the video file. Thereafter, basic units of the video file are identified. The basic units are exposition (beginning), conflict (middle), and resolution (end). Thereafter, key frames are extracted from the basic units based on at least one of audio frames, visual frames, and a combination of the visual frames and the audio frames. Then, the extracted key frames are manipulated to output a series of still images. Subsequently, narration in the form of audio or text is attached to the still images to generate at least one of comic strips and storyboards.
摘要翻译：提供了一种用于从输入视频文件生成一系列静止图像的方法，系统和计算机程序产品代码。一系列静止图像可以包括但不限于漫画和故事板。该方法包括从视频文件中提取音视频帧。此后，识别视频文件的基本单元。基本单位是博览会（开始），冲突（中间）和分辨率（结束）。此后，基于音频帧，视觉帧以及视觉帧和音频帧的组合中的至少一个，从基本单元提取关键帧。然后，操作所提取的关键帧以输出一系列静止图像。随后，将音频或文本形式的叙述附加到静止图像以产生漫画和故事板中的至少一个。

7. 发明授权

US08956584B2 Production of polycrystalline silicon in substantially closed-loop processes that involve disproportionation operations 有权
标题翻译：在涉及歧化作业的基本闭环过程中生产多晶硅
公开(公告)号：US08956584B2
公开(公告)日：2015-02-17
申请号：US13328029
申请日：2011-12-16
申请人： Puneet Gupta , Yue Huang , Satish Bhusarapu
发明人： Puneet Gupta , Yue Huang , Satish Bhusarapu
IPC分类号： C01B33/03 , B01J8/24 , C01B33/04
CPC分类号： C01B33/027 , C01B33/03
摘要： Production of polycrystalline silicon in substantially closed-loop processes and systems is disclosed. The processes and systems generally involve disproportionation of trichlorosilane to produce silane or dichlorosilane and thermal decomposition of silane or dichlorosilane to produce polycrystalline silicon.
摘要翻译：公开了在基本闭环过程和系统中生产多晶硅。方法和系统通常涉及三氯硅烷的歧化以产生硅烷或二氯硅烷以及硅烷或二氯硅烷的热分解以产生多晶硅。

8. 发明授权

US08949768B2 Standard cells having transistors annotated for gate-length biasing 有权
标题翻译：具有用于栅极长度偏置的晶体管的标准单元
公开(公告)号：US08949768B2
公开(公告)日：2015-02-03
申请号：US13620669
申请日：2012-09-14
申请人： Puneet Gupta , Andrew B. Kahng
发明人： Puneet Gupta , Andrew B. Kahng
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081 , G06F17/5063 , G06F17/5068 , G06F2217/78
摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.
摘要翻译：公开了一种标准细胞库。标准单元库包含其中注释至少一个单元中的至少一个晶体管用于栅长度偏置的单元。栅极长度偏置包括栅极长度的修改，以便改变修改的栅极长度的速度或功率消耗。标准单元库是用于制造半导体器件（例如，作为半导体芯片的结果）的方法，通过制造在几何形状的一个或多个布局上限定的特征。注释用于在使用用于制造半导体器件的几何形状之前识别哪些晶体管栅极特征将被修改。

9. 发明授权

US08524048B2 Processes for recovering silane from heavy-ends separation operations 有权
标题翻译：从重尾分离操作回收硅烷的方法
公开(公告)号：US08524048B2
公开(公告)日：2013-09-03
申请号：US12898494
申请日：2010-10-05
申请人： Zhihui Gu , Timothy D. Truong , Puneet Gupta
发明人： Zhihui Gu , Timothy D. Truong , Puneet Gupta
IPC分类号： B01D3/14 , C01B33/04 , F25J1/00
CPC分类号： B01D3/143
摘要： Processes and systems for purifying silane-containing streams are disclosed with relatively less silane being lost in impurity streams by use of distillation and/or condensation operations.
摘要翻译：公开了用于纯化含硅烷料流的方法和系统，通过使用蒸馏和/或冷凝操作，相对较少的硅烷在杂质流中损失。

10. 发明授权

US08490043B2 Standard cells having transistors annotated for gate-length biasing 失效
公开(公告)号：US08490043B2
公开(公告)日：2013-07-16
申请号：US12717887
申请日：2010-03-04
申请人： Puneet Gupta , Andrew B. Kahng
发明人： Puneet Gupta , Andrew B. Kahng
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5063 , G06F17/5068 , G06F2217/78
摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

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