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61. 发明申请

US20080302412A1 PHOTOVOLTAIC POWER DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：光伏电源装置及其制造方法
公开(公告)号：US20080302412A1
公开(公告)日：2008-12-11
申请号：US11935882
申请日：2007-11-06
申请人： Hsi-Chieh CHEN , Chih-Hsun CHU
发明人： Hsi-Chieh CHEN , Chih-Hsun CHU
IPC分类号： H01L31/04
CPC分类号： H01L31/0725 , H01L31/02168 , H01L31/022433 , H01L31/18 , Y02E10/50
摘要： A photovoltaic power device is provided. The photovoltaic power device includes a donor substrate, a first emitting substrate; a second emitting substrate, a first anti-reflection layer, a first metal electrode, a second metal electrode and a second anti-reflection layer. In the photovoltaic power device, the first and the second emitting substrate are disposed in the opposite sides of the donor substrate to generate two electronic flows, and the first metal electrode is insulated from the second metal electrode by the second anti-reflection layer.
摘要翻译：提供了一种光伏发电装置。光伏功率器件包括施主衬底，第一发光衬底; 第二发光基板，第一防反射层，第一金属电极，第二金属电极和第二防反射层。在光伏功率器件中，第一和第二发光衬底设置在供体衬底的相对侧，以产生两个电子流，并且第一金属电极通过第二抗反射层与第二金属电极绝缘。

62. 发明申请

US20080035989A1 Fabricating process and structure of trench power semiconductor device 审中-公开
标题翻译：沟槽功率半导体器件的制造工艺和结构
公开(公告)号：US20080035989A1
公开(公告)日：2008-02-14
申请号：US11826080
申请日：2007-07-12
申请人： Kou Liang Jaw , Tsung Chih Yeh , Teck Wei Chen , Tien Min Yuan , Ming Chuan Chen
发明人： Kou Liang Jaw , Tsung Chih Yeh , Teck Wei Chen , Tien Min Yuan , Ming Chuan Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A process for fabricating a trench power semiconductor device is disclosed. A first dielectric layer between the pad oxide layer and the mask oxide layer is formed so as to form a gate with a height higher than the surface of the pad oxide layer after the first dielectric layer is removed. In addition, a sidewall structure is formed at laterals of the gate protruded from the surface of the trench structure. Hence the source structure and the first conductive layer formed at the surface of the gate can be isolated through the sidewall structure. When the trench power semiconductor device is processed at high frequency, the net resistance of the gate can be reduced by the first conductive layer, and thus the electrical properties thereof can be elevated.
摘要翻译：公开了一种用于制造沟槽功率半导体器件的工艺。形成衬垫氧化物层和掩模氧化物层之间的第一电介质层，以在除去第一介电层之后形成高度高于衬垫氧化物层表面的栅极。此外，在从沟槽结构的表面突出的栅极的外侧形成侧壁结构。因此，形成在栅极表面处的源极结构和第一导电层可以通过侧壁结构隔离。当沟槽功率半导体器件以高频进行处理时，可以通过第一导电层来减小栅极的净电阻，从而可以提高其电性能。

63. 发明授权

US07282429B2 Method of manufacturing Schottky diode device 有权
标题翻译：制造肖特基二极管器件的方法
公开(公告)号：US07282429B2
公开(公告)日：2007-10-16
申请号：US11208374
申请日：2005-08-19
申请人： Shih-Chi Lai , Pei-Feng Sun , Yi Fu Chung , Jen Chieh Chang
发明人： Shih-Chi Lai , Pei-Feng Sun , Yi Fu Chung , Jen Chieh Chang
IPC分类号： H01L21/28
CPC分类号： H01L29/66143 , H01L21/32105 , H01L21/32139 , H01L27/0814
摘要： Embodiments of the invention provide a method of manufacturing a Schottky diode device. In one embodiment, the method includes: (a) providing a substrate; (b) sequentially forming a gate oxide layer and a polysilicon layer on the substrate; (c) partially oxidizing the polysilicon layer to form a poly oxide layer on the polysilicon layer; (d) forming and defining a photoresist layer on the poly oxide layer for exposing parts of the poly oxide layer; (e) etching the poly oxide layer, the polysilicon layer and the gate oxide layer via the photoresist layer for forming a poly oxide structure, a polysilicon structure and a gate oxide structure; and (f) removing the photoresist layer. The present invention introduces a poly oxide layer instead of the CVD oxide for preventing the photoresist lifting issue.
摘要翻译：本发明的实施例提供一种制造肖特基二极管器件的方法。在一个实施例中，该方法包括：（a）提供衬底; （b）在基板上依次形成栅氧化层和多晶硅层; （c）在所述多晶硅层上部分氧化所述多晶硅层以形成多晶氧化物层; （d）在所述多晶氧化物层上形成和限定光致抗蚀剂层，以暴露所述多晶氧化物层的部分; （e）经由用于形成多晶氧化物结构的光致抗蚀剂层，多晶硅结构和栅极氧化物结构蚀刻多晶氧化物层，多晶硅层和栅极氧化物层; 和（f）去除光致抗蚀剂层。本发明引入了用于防止光致抗蚀剂提升问题的多氧化物层代替CVD氧化物。

64. 发明授权

US07265024B2 DMOS device having a trenched bus structure 有权
标题翻译：具有沟槽总线结构的DMOS器件
公开(公告)号：US07265024B2
公开(公告)日：2007-09-04
申请号：US11329870
申请日：2006-01-10
申请人： Hsin-Huang Hsieh , Chiao-Shun Chuang , Chien-Ping Chang , Mao-Song Tseng
发明人： Hsin-Huang Hsieh , Chiao-Shun Chuang , Chien-Ping Chang , Mao-Song Tseng
IPC分类号： H01L21/76 , H01L21/3205 , H01L21/4763 , H01L21/336 , H01L29/76
CPC分类号： H01L29/7811 , H01L29/4232 , H01L29/4238 , H01L29/7813
摘要： A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.
摘要翻译：引入了具有沟槽总线结构的DMOS器件。沟槽总线结构包括形成在P基板上的场氧化物层和从场氧化物层的顶表面向下延伸到P衬底的下部的沟槽。形成栅极氧化层和多晶硅母线，以填充沟槽作为总线结构的主要部分。此外，在多晶硅总线和场氧化物层的顶部形成隔离层和金属线。在隔离层中形成开口以形成多晶硅母线和金属线之间的连接。在具体实施例中，同时形成DMOS器件的总线沟槽和栅极沟槽，同时形成多晶硅母线和栅电极。因此，总线结构能够形成DMOS晶体管，而不需要用于定义多晶硅总线位置的任何光刻步骤。

65. 发明申请

US20070134882A1 Method for fabicating trench metal-oxide-semiconductor field effect transistor 有权
标题翻译：用于制造沟槽金属氧化物半导体场效应晶体管的方法
公开(公告)号：US20070134882A1
公开(公告)日：2007-06-14
申请号：US11606100
申请日：2006-11-30
申请人： Hsin-Huang Hsieh , Mao-Song Tseng , Chien-Ping Chang
发明人： Hsin-Huang Hsieh , Mao-Song Tseng , Chien-Ping Chang
IPC分类号： H01L21/331
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/66727 , H01L29/66734
摘要： A method for fabricating a trench metal-oxide-semiconductor field effect transistor is disclosed. The method comprises steps of providing a substrate with an epitaxy layer thereon and etching the epitaxy layer to form a trench structure; forming a gate oxide layer on the surface of the epitaxy layer and the inner sidewalls of the trench structure and depositing a polysilicon layer to fill the trench structure; introducing a nitrogen gas and performing a driving-in procedure to form a body structure; performing an implantation procedure to form a source layer; forming a dielectric layer on the trench structure and the source layer; etching the dielectric layer and the source layer to define a source structure and form a contact region; filling the contact region with a contact structure layer; and forming a conductive metal layer on the contact structure layer and the dielectric layer.
摘要翻译：公开了一种制造沟槽金属氧化物半导体场效应晶体管的方法。该方法包括以下步骤：在衬底上提供外延层，并蚀刻外延层以形成沟槽结构; 在所述外延层的表面和所述沟槽结构的内侧壁上形成栅极氧化层，并沉积多晶硅层以填充所述沟槽结构; 引入氮气并执行驾驶过程以形成身体结构; 执行植入程序以形成源层; 在沟槽结构和源极层上形成电介质层; 蚀刻介电层和源层以限定源结构并形成接触区域; 用接触结构层填充接触区域; 以及在所述接触结构层和所述电介质层上形成导电金属层。

66. 发明申请

US20070020842A1 Method of manufacturing mask ROM 审中-公开
标题翻译：掩膜ROM的制造方法
公开(公告)号：US20070020842A1
公开(公告)日：2007-01-25
申请号：US11482715
申请日：2006-07-10
申请人： Li Tang , Shiu Lo , Chon Jou
发明人： Li Tang , Shiu Lo , Chon Jou
IPC分类号： H01L21/8238
CPC分类号： H01L27/112 , H01L27/1122
摘要： A method of manufacturing a ROM is disclosed. The method comprises steps of (a) providing a substrate and forming a plurality of gate structures on said substrate, (b) forming a first oxide layer on said substrate and said plurality of gate structures, (c) forming a mask layer on said first oxide layer and partially etching said mask layer to form a writing opening, (d) performing an ion implantation process through said mask layer, (e) removing said mask layer to expose said first oxide layer, (f) forming a second oxide layer on said first oxide layer, (g) partially etching said second oxide layer and said first oxide layer to expose a part of said substrate as a contact opening, and (h) forming a metal layer on said contact opening. Thereby, the damage of the gate structure and the problem of metal line short can be effectively avoided.
摘要翻译：公开了一种制造ROM的方法。该方法包括以下步骤：（a）提供衬底并在所述衬底上形成多个栅极结构，（b）在所述衬底和所述多个栅极结构上形成第一氧化物层，（c）在所述衬底上形成掩模层氧化层和部分蚀刻所述掩模层以形成书写开口，（d）通过所述掩模层进行离子注入工艺，（e）去除所述掩模层以暴露所述第一氧化物层，（f）在第所述第一氧化物层，（g）部分地蚀刻所述第二氧化物层和所述第一氧化物层以暴露所述衬底的一部分作为接触开口，和（h）在所述接触开口上形成金属层。因此，可以有效地避免栅极结构的损坏和金属线短路的问题。

67. 发明授权

US07118778B2 Method of applying adhesive 有权
标题翻译：涂胶的方法
公开(公告)号：US07118778B2
公开(公告)日：2006-10-10
申请号：US10668436
申请日：2003-09-22
申请人： Mifong Wu , Chung-Chih Yeh
发明人： Mifong Wu , Chung-Chih Yeh
IPC分类号： B05D5/10
CPC分类号： H01L21/02304 , C23C14/12 , H01L21/02167 , H01L21/312
摘要： An applying method for an adhesive according to an embodiment includes the following steps. First, gas is exhausted from a first exhaust pipe, so as to eliminate a part of the gas in a closed container. Next, the gas continues to be exhausted from the first exhaust pipe, so as to have the adhesive in the transmission pipeline become bubbled, and also to convey the bubbled adhesive to reach the supply vent. Later, gas is exhausted from the second exhaust pipe and continues to be exhausted from the first exhaust pipe, so as to greatly exhaust the gas in the closed container, and also to increase bubbling in the adhesive. Subsequently, the gas continues to be exhausted from the second exhaust pipe and ceases to be exhausted from the first exhaust pipe, so as to cause the adhesive to reach a gasified state. Also the gasified adhesive is supplied to the closed container from the supply vent, so that the gasified adhesive can adhere to and coat above the SiO2 layer. Finally, gas may be exhausted from the first exhaust pipe and ceases to be exhausted from the second exhaust pipe, so that the remaining gasified adhesive in the closed container is pumped out.
摘要翻译：根据实施方式的粘合剂的涂布方法包括以下步骤。首先，从第一排气管排出气体，以消除密闭容器中的一部分气体。接下来，气体继续从第一排气管排出，使得输送管道中的粘合剂变得鼓泡，并且还将鼓泡的粘合剂输送到达供气口。之后，从第二排气管排出气体，继续从第一排气管排出，从而大大排出密闭容器内的气体，并增加粘合剂的起泡。随后，气体继续从第二排气管排出，并且不再从第一排气管排出，以使粘合剂达到气化状态。此外，气化的粘合剂从供气口供应到密闭容器中，使得气化的粘合剂可以粘附并涂覆在SiO 2层上。最后，气体可以从第一排气管排出，并且不再从第二排气管排出，从而将封闭容器中剩余的气化粘合剂抽出。

68. 发明授权

US07045435B1 Shallow trench isolation method for a semiconductor wafer 有权
标题翻译：半沟槽的浅沟槽隔离方法
公开(公告)号：US07045435B1
公开(公告)日：2006-05-16
申请号：US09187197
申请日：1998-11-03
申请人： Jacson Liu
发明人： Jacson Liu
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L21/3086 , H01L21/31053
摘要： The present invention relates to a shallow trench isolation method of a semiconductor wafer which fills dielectric material into shallow trenches between components on the surface of the semiconductor wafer to electrically isolate the components. This method can prevent dishing phenomenon from occurring over the surface of some wider shallow trenches when a chemical-mechanical polishing method is used to polish the surface of the dielectric material filled in each shallow trench. The method comprises: (1) choosing the shallow trenches with widths greater than a predetermined size and generating at least one dummy in each chosen shallow trench to form a plurality of new trenches with widths less than the predetermined size; (2) covering the surface of the semiconductor wafer with dielectric material to form a dielectric layer; (3) condensing the dielectric layer; (4) polishing the surface of the dielectric layer filled in all the shallow trenches to align the surface of the dielectric material with the surface of the components on the semiconductor wafer.
摘要翻译：本发明涉及半导体晶片的浅沟槽隔离方法，其将电介质材料填充到半导体晶片表面上的部件之间的浅沟槽中以使部件电隔离。当使用化学机械抛光方法来抛光填充在每个浅沟槽中的介电材料的表面时，该方法可以防止在一些较宽的浅沟槽的表面上发生凹陷现象。该方法包括：（1）选择宽度大于预定尺寸的浅沟槽，并在每个选择的浅沟槽中产生至少一个虚拟，以形成具有小于预定尺寸的宽度的多个新沟槽; （2）用电介质材料覆盖半导体晶片的表面以形成电介质层; （3）冷凝电介质层; （4）抛光填充在所有浅沟槽中的电介质层的表面，以将电介质材料的表面与半导体晶片上的部件的表面对准。

69. 发明申请

US20060091589A1 Monitoring method for furnace apparatus 审中-公开
标题翻译：炉装置监控方法
公开(公告)号：US20060091589A1
公开(公告)日：2006-05-04
申请号：US11202734
申请日：2005-08-12
申请人： Ming-Hung Chiu , Pei-Feng Sun , Kuo-Pin Pan , Sheng-Lung Wu
发明人： Ming-Hung Chiu , Pei-Feng Sun , Kuo-Pin Pan , Sheng-Lung Wu
IPC分类号： C21D11/00
CPC分类号： F27B17/0025 , C21D11/00 , F27D19/00 , F27D21/0014 , F27D21/04 , H01L21/67109 , H01L21/67248
摘要： The present invention relates to a monitoring method for a furnace apparatus. The monitoring method includes powering on the furnace apparatus to a specific power value; recording the rate of increase of the temperature of the furnace apparatus; and comparing the rate of increase of the temperature with a predetermined threshold value, wherein the furnace apparatus is to be replaced when the rate of increase of the temperature of the furnace apparatus is less than the predetermined threshold value.
摘要翻译：本发明涉及炉装置的监视方法。监测方法包括将炉装置上电到特定功率值; 记录炉装置温度升高的速度; 以及将所述温度的增加率与预定阈值进行比较，其中当所述炉装置的温度升高速度小于所述预定阈值时，所述炉设备将被更换。

70. 发明申请

US20060046389A1 Manufacturing process and structure of integrated circuit 有权
标题翻译：集成电路的制造工艺和结构
公开(公告)号：US20060046389A1
公开(公告)日：2006-03-02
申请号：US11035700
申请日：2005-01-14
申请人： Hsin-Huang Hsieh , Chien-Ping Chang , Mao-Song Tseng , Tien-Min Yuan
发明人： Hsin-Huang Hsieh , Chien-Ping Chang , Mao-Song Tseng , Tien-Min Yuan
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/823437 , H01L27/0266 , H01L27/0883 , H01L29/66734 , H01L29/7803 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a manufacturing process and the structure of an integrated circuit. In one embodiment, one polysilicon layer deposition and one polysilicon layer etching are used to form the gate of a trench device and the polysilicon layer of a planar device simultaneously. The present invention not only has overcome the problem of the electric leakage, but also has the advantages of withstanding a higher voltage, reducing the relevant cost and increasing the yields. The present invention possesses the outstanding technical features in the field of the power device.
摘要翻译：本发明提供一种集成电路的制造工艺和结构。在一个实施例中，使用一个多晶硅层沉积和一个多晶硅层蚀刻来同时形成沟槽器件的栅极和平面器件的多晶硅层。本发明不仅克服了漏电问题，而且具有耐高压，降低相关成本，提高产量的优点。本发明在功率器件领域具有突出的技术特点。

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