专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US6065033A Wallace-tree multipliers using half and full adders 失效
标题翻译：华莱士树乘法器使用半和全加法器
公开(公告)号：US6065033A
公开(公告)日：2000-05-16
申请号：US808070
申请日：1997-02-28
申请人： Norman P. Jouppi
发明人： Norman P. Jouppi
IPC分类号： G06F7/53 , G06F7/52 , G06F7/527 , G06F7/50
CPC分类号： G06F7/5318
摘要： An apparatus sums a plurality of columns of binary bits to produce a plurality of partial sum and carry bits. The bits of a particular column being of the same order of magnitude, and the bits of different columns differing in orders of magnitude. The apparatus includes one or more full adder. Each full adder receives three bits as an input to produce a first sum bit and a first carry bit as output. The apparatus also includes one or more half adders. Each half adder receives two bits as input to produce a second sum bit and a second carry bit as output. The full adders and half adder are interconnected as a plurality of interconnecting column adders. Each column adder sums bits of the input of at least one column and generates a partial sum and carry bit. Each column adder has a plurality of stages. A plurality of conductors interconnect the stages of each column adder with other stages in the same column adder and with stages in other adjacent column adders.
摘要翻译：一种装置对多列二进制位进行求和以产生多个部分和和进位。特定列的位具有相同的数量级，并且不同列的位在数量级上不同。该装置包括一个或多个全加器。每个全加器接收三位作为输入，以产生第一和位和第一进位位作为输出。该装置还包括一个或多个半加法器。每个半加法器接收两位作为输入，以产生第二和位和第二进位位作为输出。全加法器和半加法器互连为多个互连列加法器。每列加法器将至少一列的输入的比特相加并产生部分和和进位。每列加法器具有多个级。多个导体将每列加法器的各级与同一列加法器中的其它级互相连接，并在其他相邻列加法器中将级互连。

52. 发明授权

US5682545A Microcomputer having 16 bit fixed length instruction format 失效
标题翻译：微电脑具有16位固定长度指令格式
公开(公告)号：US5682545A
公开(公告)日：1997-10-28
申请号：US475459
申请日：1995-06-07
申请人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
发明人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38 , G01F15/00
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.
摘要翻译：这里公开了采用通用寄存器方法的微计算机MCU。微型计算机能够使用效率低且系统成本低的程序容量小或高程序存储器，同时具有简化指令解码的优点，如具有现有技术的固定长度指令格式的RISC机器，通过采用固定长度指令格式，其具有功率2但是比馈送到指令执行装置的最大数据字长度的位数更小的位数。并且，通过注意码位来执行编码除法的控制。

53. 发明授权

US5583804A Data processing using multiply-accumulate instructions 失效
标题翻译：使用多重累加指令进行数据处理
公开(公告)号：US5583804A
公开(公告)日：1996-12-10
申请号：US379014
申请日：1995-01-27
申请人： David J. Seal , Guy Larri , David V. Jaggar
发明人： David J. Seal , Guy Larri , David V. Jaggar
IPC分类号： G06F7/52 , G06F7/523 , G06F7/527 , G06F7/544 , G06F9/302 , G06F9/305 , G06F17/10 , G06F7/38
CPC分类号： G06F7/5443 , G06F9/30014
摘要： A data processing system is described utilizes a multiplier-accumulator 108 that performs both a first class of multiply-accumulate instructions and a second class of multiply-accumulate instructions. The first class of multiply-accumulate instructions are of the form N*N+N.fwdarw.N and the second class of multiply-accumulate instructions are of the form N*N+2N.fwdarw.2N. The second class of multiply-accumulate instructions provide a greater precision of arithmetic in a single instruction and avoid the use of excessive instruction set space by being constrained that the result is written back into the two registers from which the 2N-bit accumulate value was taken. The multiplier-accumulator also provides N*N.fwdarw.N and N*N.fwdarw.2N multiplication operations.
摘要翻译：描述了一种数据处理系统，其利用执行第一类乘法累加指令和第二类乘法累加指令的乘法器 - 累加器108。第一类乘法累加指令的格式为N * N + N> N，第二类乘法累加指令的格式为N * N + 2N-> 2N。第二类乘法累加指令在单个指令中提供更高的算术精度，并避免使用过多的指令集空间来限制结果被写回到采用2N位累加值的两个寄存器中。乘法器累加器还提供N * N> N和N * N> 2N乘法运算。

54. 发明授权

US5452241A System for optimizing argument reduction 失效
标题翻译：用于优化参数减少的系统
公开(公告)号：US5452241A
公开(公告)日：1995-09-19
申请号：US209589
申请日：1994-03-14
申请人： Bernard Desrosiers , Louis Didier , Didier Pinchon , Andre Steimle
发明人： Bernard Desrosiers , Louis Didier , Didier Pinchon , Andre Steimle
IPC分类号： G06F7/38 , G06F7/483 , G06F7/487 , G06F7/52 , G06F7/527 , G06F7/533 , G06F7/548 , G06F17/10 , G06F7/00
CPC分类号： G06F7/4876 , G06F7/548 , G06F7/49942
摘要： A method for approximating mathematical functions using polynomial expansions is implemented in a numeric processing system. A partial remainder operation is set forth for high accuracy reduction of polynomials whose arguments are greater than pi/4. The method may be practiced in a processor having a bus of approximately half the width of the precision of the desired result. Temporary registers are utilized for the storage of intermediate results. Full bus width accuracy is obtained through successive half bus width operations.
摘要翻译：在数字处理系统中实现使用多项式扩展近似数学函数的方法。为了高精度降低参数大于pi / 4的多项式，提出了部分余数运算。该方法可以在具有所需结果的精度的大约一半宽度的总线的处理器中实现。临时寄存器用于存储中间结果。通过连续的半总线宽度操作获得完整的总线宽度精度。

55. 发明授权

US5241493A Floating point arithmetic unit with size efficient pipelined multiply-add architecture 失效
标题翻译：浮动点算术单元，尺寸有效的管道多用途建筑
公开(公告)号：US5241493A
公开(公告)日：1993-08-31
申请号：US807697
申请日：1991-12-16
申请人： Tan V. Chu , Faraydon O. Karim , Christopher H. Olson
发明人： Tan V. Chu , Faraydon O. Karim , Christopher H. Olson
IPC分类号： G06F7/487 , G06F7/527 , G06F7/533 , G06F7/544
CPC分类号： G06F7/5443 , G06F2207/386 , G06F2207/3884 , G06F7/483
摘要： An architecture and method relating to a floating point operation which performs the mathematical computation of A*B+C. The multiplication is accomplished in two or more stages, each stage involving corresponding sets of partial products and concurrently accomplished incremental summations. A pipelined architecture provides for the summation of the least significant bits of an intermediate product with operand C at a stage preceding entry into a full adder. Thereby, a significant portion of the full adder can be replaced by a simpler and smaller incrementer circuit. Partitioning of the multiplication operation into two or more partial product operations proportionally reduces the size of the multiplier required. Pipelining and concurrence execution of multiplication and addition operation in the multiplier provides in two cycles the results of the mathematical operation A*B+C while using a full adder of three-quarters normal size.

56. 发明授权

US5142490A Multiplication circuit with storing means 失效
标题翻译：具有存储装置的乘法电路
公开(公告)号：US5142490A
公开(公告)日：1992-08-25
申请号：US617440
申请日：1990-11-19
申请人： Yoshiki Tsujihashi , Kazuhiro Sakashita
发明人： Yoshiki Tsujihashi , Kazuhiro Sakashita
IPC分类号： G06F7/533 , G06F7/508 , G06F7/52 , G06F7/527 , G06F7/53
CPC分类号： G06F7/5312 , G06F2207/3884
摘要： The multiplication circuit is formed in such a manner that the intermediate sums of partial products are divided into a lower places group and a higher places group and the operations for obtaining the products of the lower places group alone of the intermediate sums already found are carried out parallel to the processing for obtaining the higher places group of the intermediate sums to obtain the higher products thereafter, noting to the fact that the intermediate sums of partial products are found sequentially from lower places to higher places. By adopting such an arrangement, the operations for obtaining the higher places group of the intermediate sums can be processed in parallel with the operations for obtaining the products of the lower places group of the intermediate sums already found, and the higher products are found thereafter. Therefore, the time required for the former-stage processing and that required for the latter-stage processing can be made more uniform.
摘要翻译：乘法电路形成为使得部分乘积的中间和被分成较低的位置组和较高的位置组，并且仅执行已经找到的中间和的单个下位组的乘积的操作平行于获得中间金额的较高地区组的处理以获得其后的较高产品，注意到从较低的地方到更高的地方依次找到部分产品的中间数量的事实。通过这样的安排，可以与获得已经找到的中间数量的下位组的产品的操作并行地获得用于获得中间数额的较高地方组的操作，并且之后发现较高的产品。因此，可以使后期处理所需的时间和后期处理所需的时间更均匀。

57. 发明授权

US4958313A CMOS parallel-serial multiplication circuit and multiplying and adding stages thereof 失效
标题翻译： CMOS并行乘法电路及其相乘和相加
公开(公告)号：US4958313A
公开(公告)日：1990-09-18
申请号：US307125
申请日：1989-02-06
申请人： Arnold Uhlenhoff
发明人： Arnold Uhlenhoff
IPC分类号： G06F7/533 , G06F7/50 , G06F7/506 , G06F7/508 , G06F7/52 , G06F7/527
CPC分类号： G06F7/5275 , G06F7/503 , G06F2207/3872
摘要： An integrated CMOS multiplication circuit is operated in a parallel-serial mode and executes binary multiplication of a multiplicand and multiplier within the period of a system clock signal by an improved implementation of the two's complement method. The multiplication circuit includes an input shift register for receiving the multiplicand bits in parallel and reading them out serially as clocked by an internal clock signal of higher frequency than the system clock signal, a single chain of multiplying stages each receiving a respective one of the multiplier bits and the serially read-out multiplicand bits and performing successive partial product operations thereon, a parallel adder having a corresponding number of adding stages for successively adding the sum and carry bit outputs of the multiplying stages, an output shift register for serially receiving the output bits of the parallel adder, and a clock driver which generates the higher frequency internal clock signal from the system clock signal. Specific configurations are provided for CMOS circuits implementing the improved parallel-serial multiplier. The clock driver preferably uses a ring oscillator to derive the higher frequency internal clock signal.
摘要翻译：集成CMOS乘法电路以并行串行模式工作，并通过二进制补码方法的改进实现，在系统时钟信号的周期内执行乘法器和乘法器的二进制相乘。乘法电路包括：输入移位寄存器，用于并行地接收被乘数位，并以与系统时钟信号相比频率高的内部时钟信号按时钟顺序读出它们;单个乘法级链，每个接收乘法器中的相应一个乘法器位和串行读出被乘数位，并对其进行连续的部分乘积运算，并行加法器具有用于连续地相加和乘法运算的输出的相加的加法级数，用于串行地接收输出的输出移位寄存器并行加法器的位，以及从系统时钟信号产生较高频率的内部时钟信号的时钟驱动器。为实现改进的并行串行乘法器的CMOS电路提供了具体的配置。时钟驱动器优选地使用环形振荡器来导出较高频率的内部时钟信号。

58. 发明授权

US4901267A Floating point circuit with configurable number of multiplier cycles and variable divide cycle ratio 失效
标题翻译：浮点电路，具有可配置的乘法器周期数和可分的分频周期比
公开(公告)号：US4901267A
公开(公告)日：1990-02-13
申请号：US167802
申请日：1988-03-14
申请人： Mark Birman , George K. Chu , Fred A. Ware , Selfia Halim
发明人： Mark Birman , George K. Chu , Fred A. Ware , Selfia Halim
IPC分类号： G06F7/487 , G06F1/12 , G06F7/527 , G06F7/53 , G06F7/535 , G06F7/537 , G06F7/552 , G06F7/57 , G06F9/302 , G06F9/38
CPC分类号： G06F9/3885 , G06F1/12 , G06F7/483 , G06F7/57 , G06F9/30014 , G06F2207/382 , G06F2207/3884
摘要： The present invention optimizes the number and ratio of cycles required among the divide/square root unit, multiplier unit and ALU. An intermediate latch with its own clock is provided at the output of the multiplier half-array in the intermediate stage to feed back data for a second pass for double-precision numbers. The multiplier can then be adjusted for either two-cycle latency mode (for optimizing double-precision multiplies) or three-cycle latency mode (for optimizing single-precision multiplies). A separate divide clock is used for the divide/square root unit, and is synchronized with the multiplier cycle clock on input and output. This allows the divide time to be optimized so that it requires fewer clock cycles when a longer multiplier clock cycle time is used.
摘要翻译：本发明优化了除法/平方根单元，乘法器单元和ALU之间所需的周期数和比率。在中间级的乘法器半阵列的输出处提供具有其自己的时钟的中间锁存器，以反馈用于双精度数字的第二遍的数据。然后可以针对两周期延迟模式（优化双精度乘法）或三周期延迟模式（用于优化单精度乘数）来调整乘数。分频/平方根单位使用单独的分频时钟，并与输入和输出的乘法器周期时钟同步。这样可以优化分频时间，以便在使用较长的乘法器时钟周期时，需要较少的时钟周期。

59. 发明授权

US4879676A Method and apparatus for precise floating point exceptions 失效
标题翻译：精确浮点异常的方法和装置
公开(公告)号：US4879676A
公开(公告)日：1989-11-07
申请号：US161543
申请日：1988-02-29
申请人： Craig C. Hansen
发明人： Craig C. Hansen
IPC分类号： G06F7/00 , G06F7/38 , G06F7/485 , G06F7/487 , G06F7/527 , G06F7/53 , G06F7/57 , G06F7/76 , G06F9/302 , G06F9/38
CPC分类号： G06F7/483 , G06F9/30014 , G06F9/3836 , G06F9/3861 , G06F2207/3884 , G06F7/4991 , G06F7/49942
摘要： In data processing systems of the type operable to perform floating point computations there is provided a method, and apparatus implementing that method, for predicting, in advance of the floating point computation, whether or not the computation will produce a floating point exception (e.g., overflow, underflow, etc.). The prediction method includes the steps of combining the exponent fields of the operands of the computation in a manner dictated by the type of operation (i.e., add, subtract, multiply, etc.), and comparing that combination, together with an indication of the computation to be performed (e.g., add, substract, multiply, or divide), to obtain an indication of the possibility of the computation ending in a floating point exception. If an exception is predicted, the indication can be used to halt other data processing operations until completion of the computation so that, in the event the computation actually results in a floating point exception, the handling of the exception can be accomplished with a minimum of effort.

60. 发明授权

US4845659A Accelerated validity response permitting early issue of instructions dependent upon outcome of floating point operations 失效
标题翻译：加速的有效性响应允许早期发布依赖于浮点运算结果的指令
公开(公告)号：US4845659A
公开(公告)日：1989-07-04
申请号：US896879
申请日：1986-08-15
申请人： David A. Hrusecky
发明人： David A. Hrusecky
IPC分类号： G06F7/38 , G06F7/485 , G06F7/527 , G06F7/533 , G06F7/57 , G06F9/302 , G06F9/32 , G06F9/38
CPC分类号： G06F7/483 , G06F9/30014 , G06F9/30094 , G06F9/3844 , G06F2207/3844 , G06F2207/3884 , G06F7/49905
摘要： Apparatus and method for accelerating a validity response provided by a floating point unit assures the validity of the present state of a condition code and an interrupt signal before the completion of a floating point arithmetic instruction whose result affects the condition code and interrupt signal. The accelerated validity response is derived from an evaluation of the exponents, signs, and fractions contained in the operands of a currently-executing floating point arithmetic operation which is made prior to or during execution of the instruction. Also provided is the capability of setting the condition code prior to the completion of certain add class floating point instructions where one of those instructions stimulates an early validity response. An accelerated interrupt request is also provided in synchronism with an accelerated validity response for certain floating point add and subtract instructions.
摘要翻译：用于加速由浮点单元提供的有效性响应的装置和方法确保在结果影响条件码和中断信号的浮点算术指令完成之前条件码和中断信号的当前状态的有效性。加速的有效性响应是从在指令执行之前或期间执行的当前执行的浮点算术运算的操作数中包含的指数，符号和分数的评估得出的。还提供了在完成某些附加类浮点指令之前设置条件代码的能力，其中这些指令之一刺激早期有效性响应。加速中断请求也与某些浮点加法和减法指令的加速有效性响应同步提供。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式