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1. 发明授权

US5506976A Branch cache 失效
标题翻译：分支缓存
公开(公告)号：US5506976A
公开(公告)日：1996-04-09
申请号：US303230
申请日：1994-09-08
申请人： David V. Jaggar
发明人： David V. Jaggar
IPC分类号： G06F12/08 , G06F9/38 , G06F13/00
CPC分类号： G06F9/3806 , G06F9/3844
摘要： A pipeline processor 2 having an associated branch cache 4 is provided. Each cache line 12 of the branch cache stores a cache TAG, a next branch data value R, a target address value TA and a target instruction value TI. The next branch data value indicates when the next branch instruction will be encountered in the stream of instructions fed to the pipeline processor. This data is used such that following a branch cache hit, no further reading of the branch cache is made until the next branch data indicates that the next branch instruction should have been reached. At this stage, the branch cache 4 is read to see if it contains corresponding data for that next branch instruction that will avoid the need to decode that next branch instruction before instructions from the target address of that branch instruction can be fed into the pipeline. The avoiding of the need to read the branch cache for every instruction fed into the pipeline saves power.
摘要翻译：提供具有相关联的分支高速缓冲存储器4的流水线处理器2。分支高速缓存行的每个高速缓存行12存储高速缓存器TAG，下一个分支数据值R，目标地址值TA和目标指令值TI。下一个分支数据值指示何时在馈送到流水线处理器的指令流中遇到下一个分支指令。使用该数据使得在分支高速缓存命中之后，不再进一步读取分支高速缓存，直到下一分支数据指示应当已经到达下一分支指令为止。在这个阶段，读取分支高速缓冲存储器4，以查看它是否包含用于该下一个分支指令的对应数据，该指令将避免在来自该分支指令的目标地址的指令可以被馈送到流水线中之前对该下一个分支指令进行解码。为了节省能源，避免了为每个提供给管道的指令读取分支缓存的需要。

2. 发明授权

US5583804A Data processing using multiply-accumulate instructions 失效
标题翻译：使用多重累加指令进行数据处理
公开(公告)号：US5583804A
公开(公告)日：1996-12-10
申请号：US379014
申请日：1995-01-27
申请人： David J. Seal , Guy Larri , David V. Jaggar
发明人： David J. Seal , Guy Larri , David V. Jaggar
IPC分类号： G06F7/52 , G06F7/523 , G06F7/527 , G06F7/544 , G06F9/302 , G06F9/305 , G06F17/10 , G06F7/38
CPC分类号： G06F7/5443 , G06F9/30014
摘要： A data processing system is described utilizes a multiplier-accumulator 108 that performs both a first class of multiply-accumulate instructions and a second class of multiply-accumulate instructions. The first class of multiply-accumulate instructions are of the form N*N+N.fwdarw.N and the second class of multiply-accumulate instructions are of the form N*N+2N.fwdarw.2N. The second class of multiply-accumulate instructions provide a greater precision of arithmetic in a single instruction and avoid the use of excessive instruction set space by being constrained that the result is written back into the two registers from which the 2N-bit accumulate value was taken. The multiplier-accumulator also provides N*N.fwdarw.N and N*N.fwdarw.2N multiplication operations.
摘要翻译：描述了一种数据处理系统，其利用执行第一类乘法累加指令和第二类乘法累加指令的乘法器 - 累加器108。第一类乘法累加指令的格式为N * N + N> N，第二类乘法累加指令的格式为N * N + 2N-> 2N。第二类乘法累加指令在单个指令中提供更高的算术精度，并避免使用过多的指令集空间来限制结果被写回到采用2N位累加值的两个寄存器中。乘法器累加器还提供N * N> N和N * N> 2N乘法运算。

3. 发明授权

US5568646A Multiple instruction set mapping 失效
标题翻译：多指令集映射
公开(公告)号：US5568646A
公开(公告)日：1996-10-22
申请号：US308838
申请日：1994-09-19
申请人： David V. Jaggar
发明人： David V. Jaggar
IPC分类号： G06F9/38 , G06F9/30 , G06F9/318 , G06F9/00
CPC分类号： G06F9/30174 , G06F9/30189 , G06F9/30196
摘要： A data processing system is described utilising multiple instruction sets. The program instruction words are supplied to a processor core 2 via an instruction pipeline 6. As program instruction words of a second instruction set pass along the instruction pipeline, they are mapped to program instruction words of the first instruction set. The second instruction set has program instruction words of a smaller bit size than those of the first instruction set and is a subset of the first instruction set. Smaller bit size improves code density, whilst the nature of the second instruction set as a subset of the first instruction set enables a one-to-one mapping to be efficiently performed and so avoid the need for a dedicated instruction decoder for the second instruction set.
摘要翻译：利用多个指令集描述数据处理系统。程序指令字通过指令流水线6提供给处理器核心2.随着第二指令集的程序指令字沿着指令流水线传递，它们被映射到第一指令集的程序指令字。第二指令集具有比第一指令集小的位大小的程序指令字，并且是第一指令集的子集。较小的位大小提高了代码密度，而作为第一指令集的子集的第二指令集的性质使得能够有效地执行一对一映射，因此避免了对于第二指令集的专用指令解码器的需要。

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