专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US07397882B2 Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion 有权
标题翻译：数字锁相电路能够处理以突发方式提供的输入时钟信号
公开(公告)号：US07397882B2
公开(公告)日：2008-07-08
申请号：US10671593
申请日：2003-09-29
申请人： Ichiro Yokokura , Yuji Obana , Hideaki Mochizuki
发明人： Ichiro Yokokura , Yuji Obana , Hideaki Mochizuki
IPC分类号： H03D3/24
CPC分类号： H03L7/0993 , H03L7/107 , H04J3/076
摘要： A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase comparing part compares the phase of the output clock signal with the phase of the input clock signal. A phase comparison result detecting part outputs an INC/DEC request signal for controlling a division operation based on a phase comparison signal. An execution rate computing part computes a phase difference between the input clock signal and the output clock signal based on the INC/DEC request signal and outputs an execution rate corresponding to the phase difference. A clock generating part controls a division operation for the master clock signal in accordance with the INC/DEC request signal and changes phase absorption speed of the output clock signal in accordance with the execution rate.
摘要翻译：数字锁相电路提供输出时钟信号，其输出时钟信号的相位与期望的相位吸收特性水平下的输入时钟信号的相位同步，即使以突发方式提供输入时钟信号。相位比较部分将输出时钟信号的相位与输入时钟信号的相位进行比较。相位比较结果检测部分输出用于根据相位比较信号控制除法运算的INC / DEC请求信号。执行率计算部分根据INC / DEC请求信号计算输入时钟信号和输出时钟信号之间的相位差，并输出与相位差对应的执行速率。时钟产生部分根据INC / DEC请求信号控制主时钟信号的除法运算，并根据执行速率改变输出时钟信号的相位吸收速度。

52. 发明授权

US07133397B2 Time division duplex system utilizing global positioning system timing signals for access point synchronization 有权
公开(公告)号：US07133397B2
公开(公告)日：2006-11-07
申请号：US09948615
申请日：2001-09-07
申请人： Delon K. Jones , James M. Simkins
发明人： Delon K. Jones , James M. Simkins
IPC分类号： H04J3/06
CPC分类号： H04J3/0644 , H03L7/0993 , H04J3/0688
摘要： A method and apparatus for Time Division Duplex (TDD) synchronization of Access Points (APEs) uses the 1 pulse-per-second timing pulses of the Global Positioning System (GPS) and synchronization state machines for its Time Division Multiple Access (TDMA) structure. As a result, the present invention obviates the need for expensive voltage-controlled oscillators used by the prior art, and achieves stable timing accuracy within approximately 7.5 minutes, as opposed to the 12 to 24-hour period needed by prior art methods.

53. 发明授权

US06998886B1 Apparatus and method for PLL with equalizing pulse removal 有权
标题翻译： PLL的均衡脉冲去除装置和方法
公开(公告)号：US06998886B1
公开(公告)日：2006-02-14
申请号：US10881483
申请日：2004-06-30
申请人： Hon K. Chiu
发明人： Hon K. Chiu
IPC分类号： H03L7/06
CPC分类号： H03L7/095 , H03L7/0891 , H03L7/0993
摘要： A phase-locked loop circuit is arranged for equalizing pulse removal. The phase-locked loop circuit includes a multi-phase pulse generator circuit that is arranged to provide a feedback signal and a gate signal from an output of a voltage-controlled oscillation circuit. The gate signal leads the feedback signal by approximately one-fourth of a period. Also, an equalizing pulse removal logic circuit is arranged to provide a sync gate signal from the feedback signal, the gate signal, and a sync signal. The sync gate signal is provided such that, if the sync signal includes equalizing pulses, the sync gate signal corresponds to an inactive logic level during the equalizing pulses. A phase-frequency detector of the phase-locked loop circuit is gated such that the phase-frequency detector is not changed by the sync signal if the sync gate signal corresponds to the inactive logic level.
摘要翻译：设置了锁相环电路，用于均衡脉冲去除。锁相环电路包括多相脉冲发生器电路，其被配置为从压控振荡电路的输出提供反馈信号和栅极信号。门信号将反馈信号引导约四分之一的周期。此外，均衡脉冲去除逻辑电路被布置成从反馈信号，门信号和同步信号提供同步门信号。提供同步门信号，使得如果同步信号包括均衡脉冲，则同步门信号在均衡脉冲期间对应于非活动逻辑电平。锁相环电路的相位频率检测器被选通，使得如果同步门信号对应于不活动逻辑电平，则相位 - 频率检测器不被同步信号改变。

54. 发明授权

US06608876B2 Phase control circuit and phase control method 有权
标题翻译：相位控制电路及相位控制方式
公开(公告)号：US06608876B2
公开(公告)日：2003-08-19
申请号：US09139324
申请日：1998-08-25
申请人： Kiyohiko Yamazaki
发明人： Kiyohiko Yamazaki
IPC分类号： H03D324
CPC分类号： H03L7/089 , H03D13/004 , H03L7/095 , H03L7/0993 , H03L7/18 , H04L7/0083 , H04L7/0331
摘要： The present invention relates to the control of a phase control circuit and, more particularly, to a DPLL circuit used to accomplish synchronization when connecting a digital network connecting unit such as a digital service unit (DSU) with a radio unit such as a personal handy phone system (PHS); it prevents a problem involved in the phase control during sending or receiving. The phase control circuit has: a phase comparator circuit that compares the phase difference between a synchronizing signal and a signal to be controlled and outputs a phase control signal according to a comparison result; a phase changing circuit that changes the phase of the signal to be controlled according to the phase control signal; and a mask circuit that masks the phase control signal supplied to the phase changing circuit according to a phase control disable signal.
摘要翻译：本发明涉及相位控制电路的控制，更具体地说，涉及一种DPLL电路，用于在将诸如数字服务单元（DSU）的数字网络连接单元与诸如个人便利的无线电单元连接时实现同步电话系统（PHS）; 它可以防止在发送或接收期间相位控制中涉及的问题。相位控制电路具有：比较同步信号和被控制信号之间的相位差的相位比较器电路，并根据比较结果输出相位控制信号; 相变电路，根据相位控制信号改变要被控制的信号的相位; 以及屏蔽电路，根据相位控制禁止信号，屏蔽提供给相变电路的相位控制信号。

55. 发明授权

US06493408B1 Low-jitter data transmission apparatus 失效
标题翻译：低抖动数据传输装置
公开(公告)号：US06493408B1
公开(公告)日：2002-12-10
申请号：US09443005
申请日：1999-11-18
申请人： Eiichi Kobayashi
发明人： Eiichi Kobayashi
IPC分类号： H04L700
CPC分类号： H04L1/205 , H03L7/0993 , H03L7/18 , H03L2207/10 , H04J3/0688
摘要： For restraining jitter amount of a transmission clock signal (16) generated by a digital PLL (8), a data transmission apparatus comprises a {fraction (1/24)} clock generator (6) for dividing frequency of a receiving clock signal (4), a clock multiplier (7) for generating a reference frequency signal (18) by multiplying frequency of the output of the {fraction (1/24)} clock generator (6), and a control unit (28) for controlling a frequency multiplying ratio of the clock multiplier (7) and controlling a frequency dividing ratio of a frequency divider provided in the digital PLL (8). According to jitter amount detected by a jitter detection signal generator (19), the frequency of the reference clock signal (18) is selected among {fraction (1/12)}, ⅛ and ⅙ of the frequency of the receiving clock signal.
摘要翻译：为了抑制由数字PLL（8）产生的传输时钟信号（16）的抖动量，数据传输装置包括用于分配接收时钟信号（4）的频率的1/24时钟发生器（6），时钟乘法器（7），用于通过乘以1/24时钟发生器（6）的输出频率产生参考频率信号（18）;以及控制单元（28），用于控制时钟乘法器（7）和控制在数字PLL（8）中提供的分频器的分频比。根据由抖动检测信号发生器（19）检测到的抖动量，参考时钟信号（18）的频率在接收时钟信号的频率的1/12，1/8和⅙之间选择。

56. 发明申请

US20020051507A1 PHASE CONTROL CIRCUIT AND PHASE CONTROL METHOD 有权
标题翻译：相控电路及相位控制方法
公开(公告)号：US20020051507A1
公开(公告)日：2002-05-02
申请号：US09139324
申请日：1998-08-25
发明人： YAMAZAKI KIYOHIKO
IPC分类号： H03D003/24
CPC分类号： H03L7/089 , H03D13/004 , H03L7/095 , H03L7/0993 , H03L7/18 , H04L7/0083 , H04L7/0331
摘要： The present invention relates to the control of a phase control circuit and, more particularly, to a DPLL circuit used to accomplish synchronization when connecting a digital network connecting unit such as a digital service unit (DSU) with a radio unit such as a personal handy phone system (PHS); it prevents a problem involved in the phase control during sending or receiving. The phase control circuit has: a phase comparator circuit that compares the phase difference between a synchronizing signal and a signal to be controlled and outputs a phase control signal according to a comparison result; a phase changing circuit that changes the phase of the signal to be controlled according to the phase control signal; and a mask circuit that masks the phase control signal supplied to the phase changing circuit according to a phase control disable signal.
摘要翻译：本发明涉及相位控制电路的控制，更具体地说，涉及一种DPLL电路，用于在将诸如数字服务单元（DSU）的数字网络连接单元与诸如个人便利的无线电单元连接时实现同步电话系统（PHS）; 它可以防止在发送或接收期间相位控制中涉及的问题。相位控制电路具有：比较同步信号和被控制信号之间的相位差的相位比较器电路，并根据比较结果输出相位控制信号; 相变电路，根据相位控制信号改变要被控制的信号的相位; 以及屏蔽电路，根据相位控制禁止信号，屏蔽提供给相变电路的相位控制信号。

57. 发明授权

US06380811B1 Signal generator, and method 有权
标题翻译：信号发生器和方法
公开(公告)号：US06380811B1
公开(公告)日：2002-04-30
申请号：US09784279
申请日：2001-02-16
申请人： Michael Zarubinsky , Konstantin Berman , Eliav Zipper
发明人： Michael Zarubinsky , Konstantin Berman , Eliav Zipper
IPC分类号： H03L706
CPC分类号： H03L7/0993 , H03L7/085 , H03L7/23
摘要： A signal generator (100) receives an input clock signal (X1) at a first frequency (F1) and derives an output clock signal (Y) at a second frequency (FY). An arrangement (110) using a first intermediate signal (Z) receives the input clock signal (X1) and provides a second intermediate signal (X2) by selectively providing transitions (119) of the second intermediate signal (X2) at time intervals (T2(n)) that are determined by a variable number (A+P(n)) of periods (TZ) of the first intermediate signal (Z). The second intermediate signal (X2) has a frequency (F2) that is in average (F′2) higher than the first frequency (F1). A phase-looked loop (PLL) circuit (180) locks at this average frequency (F′2) and provides the output clock signal (Y).
摘要翻译：信号发生器（100）以第一频率（F1）接收输入时钟信号（X1），并以第二频率（FY）导出输出时钟信号（Y）。使用第一中间信号（Z）的装置（110）通过选择性地以时间间隔（T2）提供第二中间信号（X2）的转变（119）来接收输入时钟信号（X1）并提供第二中间信号（X2）（N）），其由第一中间信号（Z）的周期（TZ）的可变数（A + P（n））确定。第二中间信号（X2）具有比第一频率（F1）高的平均值（F'2）的频率（F2）。相位环路（PLL）电路（180）以该平均频率（F'2）锁定并提供输出时钟信号（Y）。

58. 发明授权

US06233297B1 Plesiochronous digital hierarchy low speed signal switching digital phase-locked loop system 失效
标题翻译：精密同步数字层级低速信号切换数字锁相环系统
公开(公告)号：US06233297B1
公开(公告)日：2001-05-15
申请号：US09074940
申请日：1998-05-08
申请人： Masaaki Itoh
发明人： Masaaki Itoh
IPC分类号： H03D324
CPC分类号： H03L7/0993 , H03L7/089 , H04J3/076
摘要： A destuff circuit using a complete secondary system DPLL enables a DPLL circuit applicable to PDH low speed signal interface unit of a transmission communication apparatus to be shared. A switching signal from a selector causes a primary random walk filter, a secondary random walk filter, and counter number of a Q counter to be changed, and also causes the rate length of a rate multiplier to be changed, thereby providing a required DPLL circuit for a respective PDH low speed signal interface.
摘要翻译：使用完整的二次系统DPLL的消除电路使得能够共享适用于传输通信装置的PDH低速信号接口单元的DPLL电路。来自选择器的切换信号导致主随机游走滤波器，二次随机游走滤波器和Q计数器的计数器数量被改变，并且还使得速率乘法器的速率长度被改变，从而提供所需的DPLL电路用于相应的PDH低速信号接口。

59. 发明授权

US4947407A Sample-and-hold digital phase-locked loop for ask signals 失效
标题翻译：采样保持用于询问信号的数字锁相环
公开(公告)号：US4947407A
公开(公告)日：1990-08-07
申请号：US391215
申请日：1989-08-08
申请人： Sergiu Silvian
发明人： Sergiu Silvian
IPC分类号： H04L27/02 , A61N1/372 , H03L7/099 , H03L7/14 , H04L7/00 , H04L27/06
CPC分类号： A61N1/3727 , H03L7/0993 , H03L7/14 , H04L27/066
摘要： A digital phase-locked looped generates a clock signal synchronized with a carrier signal modulated by amplitude shift keying (ASK). During periods when no carrier signal is present, the generated clock signal coasts at the frequency of the carrier signal most recently present, rather than trying to phase-lock on noise. A binary controlled digital oscillator generates the clock signal. A phase detector determines the difference between the phase of the carrier signal, when present, and the local clock signal. When the average amplitude of the carrier signal exceeds a prescribed threshold level, the phase detector output is sampled and passed to an integrator circuit, where the phase difference is integrated. The output of the integrator circuit is applied to a pulse generator, causing the pulse generator's duty cycle to change proportionally. In turn, the pulses are applied to the binary controlled digital oscillator, causing the frequency of the local clock signal to shift in a direction that minimizes the phase error between the local clock signal and the carrier signal. When the average amplitude of the carrier signal is less than the prescribed threshold level, the phase detector output is not smapled. In such case, the output of the integrator circuit remains at the value obtained from the most recent prior phase detector sample.

60. 发明授权

US4617520A Digital lock detector for a phase-locked loop 失效
标题翻译：用于锁相环的数字锁定检测器
公开(公告)号：US4617520A
公开(公告)日：1986-10-14
申请号：US567714
申请日：1984-01-03
申请人： Stephen N. Levine
发明人： Stephen N. Levine
IPC分类号： H03K5/26 , H03K23/66 , H03L7/06 , H03L7/099 , H04L7/033 , H03D13/00 , H03K9/06 , H03L7/00
CPC分类号： H03K23/662 , H03L7/0993 , H04L7/0331 , Y10S331/02
摘要： A digital lock detector for a phase-locked loop accumulates out-of-lock pulses which are derived from a high frequency clock signal. The out-of-lock pulses are gated by an out-of-phase indicator signal and a pulse centered around the phase-locked loop output cycles to reduce the effect of relative phase jitter between the input and output signals of the phase-locked loop. The digital lock detector utilizes two counters in series which are reset independently to provide resistance to fading signal conditions. In addition, the lock detector circuit requires several consecutive long out-of-lock indications before an out-of-lock condition is indicated.
摘要翻译：用于锁相环的数字锁定检测器累积从高频时钟信号导出的失锁脉冲。失锁脉冲由异相指示器信号和以锁相环输出周期为中心的脉冲选通，以减少锁相环输入和输出信号之间相对相位抖动的影响。数字锁定检测器利用两个串联的计数器，它们独立复位，以提供对衰落信号条件的电阻。此外，锁定检测器电路在指示失锁状态之前需要几个连续的长时间超出锁定指示。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式