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51. 发明申请

US20120139650A1 CHARGE PUMP AND PHASE DETECTION APPARATUS, PHASE-LOCKED LOOP AND DELAY-LOCKED LOOP USING THE SAME 有权
标题翻译：充电泵和相位检测装置，相位锁定环和延迟锁定环
公开(公告)号：US20120139650A1
公开(公告)日：2012-06-07
申请号：US13012512
申请日：2011-01-24
申请人： Meng-Ting TSAI , Kun-Ju Tsai , Yung-Chih Liang
发明人： Meng-Ting TSAI , Kun-Ju Tsai , Yung-Chih Liang
IPC分类号： H03J7/06 , H03D13/00 , H03L7/06 , G05F1/10
CPC分类号： H03L7/0896 , H03D13/00 , H03L7/089
摘要： A charge pump includes a first current source, a second current source, a first switch, a second switch, a third switch, a fourth switch, a reset switch, an inverse reset switch and a capacitance. The first and third switches have first terminals coupled to the first current source. The second and fourth switches have first terminals coupled to the second current source. The first, second and reset switches have second terminals coupled to a first terminal of the inverse reset switch. The reset switch has a first terminal coupled to second terminals of the third and fourth switches. The first and second switches are respectively controlled by first and second control signals, the third and fourth switches are respectively controlled by inverse signals of the first and second control signals, and the inverse reset switch is controlled by the inverse reset signal.
摘要翻译：电荷泵包括第一电流源，第二电流源，第一开关，第二开关，第三开关，第四开关，复位开关，反向复位开关和电容。第一和第三开关具有耦合到第一电流源的第一端子。第二和第四开关具有耦合到第二电流源的第一端子。第一，第二和复位开关具有耦合到反向复位开关的第一端子的第二端子。复位开关具有耦合到第三和第四开关的第二端子的第一端子。第一和第二开关分别由第一和第二控制信号控制，第三和第四开关分别由第一和第二控制信号的反相信号控制，反相复位开关由反相复位信号控制。

52. 发明授权

US08154328B1 Techniques for measuring phases of periodic signals 有权
标题翻译：测量周期信号相位的技术
公开(公告)号：US08154328B1
公开(公告)日：2012-04-10
申请号：US12814332
申请日：2010-06-11
申请人： Sudheer Vemula
发明人： Sudheer Vemula
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/089 , H03L7/095
摘要： A phase detector circuit generates a phase comparison signal based on a phase difference between first and second periodic signals during a test mode. Phases of the first and the second periodic signals do not change in response to variations in a signal generated by the phase detector circuit during the test mode. A lock generation circuit generates an output signal based on the phase comparison signal that indicates if the first and the second periodic signals are within a lock window of the lock generation circuit. The lock window of the lock generation circuit changes in response to a variation in a control signal.
摘要翻译：相位检测器电路在测试模式期间基于第一和第二周期信号之间的相位差产生相位比较信号。响应于在测试模式期间由相位检测器电路产生的信号的变化，第一和第二周期信号的相位不变化。锁产生电路基于指示第一和第二周期信号是否在锁生成电路的锁定窗口内的相位比较信号产生输出信号。锁产生电路的锁定窗口响应于控制信号的变化而改变。

53. 发明申请

US20120076180A1 PHASE-LOCKED LOOP AND RADIO COMMUNICATION DEVICE 审中-公开
标题翻译：相位锁定环路和无线电通信设备
公开(公告)号：US20120076180A1
公开(公告)日：2012-03-29
申请号：US13178922
申请日：2011-07-08
申请人： Hiroaki HOSHINO
发明人： Hiroaki HOSHINO
IPC分类号： H03L7/06 , H04B1/38
CPC分类号： H03L7/089
摘要： According to one embodiment, a phase-locked loop includes: a voltage controlled oscillator that generates an oscillation signal including an oscillation frequency corresponding to a control signal; a divider that divides the oscillation signal to generate a frequency-divided signal; a phase frequency detector that compares the phases of the frequency-divided signal and a reference signal to generate a comparison signal; a charge pump that outputs current corresponding to the comparison signal; a filter that filters the current to generate the control signal; a detection circuit that generates a detection signal when the difference between a value of a constant multiple of the frequency of the frequency-divided signal and a value of a constant multiple of the frequency of the reference signal becomes local minimum; and a phase adjustment circuit that synchronizes the phases of the frequency-divided signal and the reference signal when the detection signal is generated.
摘要翻译：根据一个实施例，锁相环包括：压控振荡器，其产生包括对应于控制信号的振荡频率的振荡信号; 分频器，其分频振荡信号以产生分频信号; 相位频率检测器，其对分频信号的相位和基准信号进行比较，生成比较信号; 输出与比较信号对应的电流的电荷泵; 滤波器，用于过滤电流以产生控制信号; 检测电路，当分频信号的频率的恒定倍数与参考信号的频率的恒定倍数的值之间的差成为局部最小时，生成检测信号; 以及相位调整电路，当产生检测信号时，使分频信号和参考信号的相位同步。

54. 发明申请

US20120051493A1 CONTINOUS HIGH-FREQUENCY EVENT FILTER 有权
标题翻译：连续高频事件滤波器
公开(公告)号：US20120051493A1
公开(公告)日：2012-03-01
申请号：US13294083
申请日：2011-11-10
申请人： Tyler Gomm , Kang Yong Kim
发明人： Tyler Gomm , Kang Yong Kim
IPC分类号： H03K23/00
CPC分类号： H03L7/0814 , G06F7/62 , G11C7/22 , G11C7/222 , H03L7/0805 , H03L7/085 , H03L7/089
摘要： A circuit and method for generating an active output signal in response to detecting N events, which are represented by an event signal. A counter circuit is configured to increment and decrement through a sequence of values in response to the event signal. Detection logic coupled to the counter circuit is configured to detect at least first and second values of the sequence. The detection logic is further configured to generate the active output signal and switch to detecting the second value in response to detecting the first value and generate the active output signal and switch to detecting the first value in response to detecting the second value. The first and second values are separated by N counts.
摘要翻译：一种用于响应于由事件信号表示的N个事件来产生有效输出信号的电路和方法。计数器电路被配置为响应于事件信号递增和递减一系列值。耦合到计数器电路的检测逻辑被配置为检测序列的至少第一和第二值。检测逻辑还被配置为产生有效输出信号并且响应于检测到第一值而切换到检测第二值，并且产生有效输出信号并且响应于检测到第二值而切换到检测第一值。第一个值和第二个值用N个数值分隔。

55. 发明申请

US20120049910A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20120049910A1
公开(公告)日：2012-03-01
申请号：US13137144
申请日：2011-07-22
申请人： Morishige Aoyama
发明人： Morishige Aoyama
IPC分类号： H03L7/08
CPC分类号： H03L7/089
摘要： A semiconductor device includes a clock-and-data recovery circuit including a phase tracking loop that generates a phase difference signal indicating a phase difference between a reception clock generated from a transmission clock and an input signal and makes the reception clock track the input signal, a frequency tracking loop that performs control to make a frequency of the reception clock track a frequency of the input signal, the clock-and-data recovery circuit being configured to extract a data signal and a synchronization clock from the input signal and to control a phase and a frequency of the reception clock, a frequency error adjuster that increases or decreases a value indicated by a frequency adjustment signal according to a frequency difference signal generated based on the phase difference signal, and an oscillator that increases or decreases a frequency of the transmission clock based on the frequency adjustment signal.
摘要翻译：半导体器件包括时钟和数据恢复电路，其包括相位跟踪环路，该相位跟踪环路产生指示从传输时钟产生的接收时钟与输入信号之间的相位差的相位差信号，并使接收时钟跟踪输入信号，执行控制以使接收时钟的频率跟踪输入信号的频率的频率跟踪环路，所述时钟和数据恢复电路被配置为从输入信号提取数据信号和同步时钟，并且控制相位和接收时钟的频率，频率误差调整器，其根据基于相位差信号产生的频差信号增加或减少由频率调整信号指示的值;以及振荡器，其增加或减少接收时钟的频率传输时钟基于频率调整信号。

56. 发明授权

US08125254B1 Techniques for configuring multi-path feedback loops 有权
标题翻译：用于配置多径反馈回路的技术
公开(公告)号：US08125254B1
公开(公告)日：2012-02-28
申请号：US12613465
申请日：2009-11-05
申请人： Weiqi Ding
发明人： Weiqi Ding
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03L2207/06
摘要： In some embodiments, a feedback loop circuit includes a phase detector, first and second charge pumps that are each coupled to receive an output signal of the phase detector, a first low pass filter, a second low pass filter coupled to an output of the second charge pump, a clock signal generation circuit having first and second control inputs, a first switch circuit coupled between the first low pass filter and the second low pass filter, and a second switch circuit coupled to the first low pass filter and the first control input of the clock signal generation circuit.
摘要翻译：在一些实施例中，反馈回路包括相位检测器，第一和第二电荷泵，每个电荷泵被耦合以接收相位检测器的输出信号，第一低通滤波器，耦合到第二低通滤波器的输出的第二低通滤波器电荷泵，具有第一和第二控制输入的时钟信号发生电路，耦合在第一低通滤波器和第二低通滤波器之间的第一开关电路，以及耦合到第一低通滤波器和第一控制输入端的第二开关电路的时钟信号发生电路。

57. 发明授权

US08098788B1 System and method for automatic leakage control circuit for clock/data recovery and charge-pump phase locked loops 有权
标题翻译：用于时钟/数据恢复和电荷泵锁相环的自动泄漏控制电路的系统和方法
公开(公告)号：US08098788B1
公开(公告)日：2012-01-17
申请号：US12125016
申请日：2008-05-21
申请人： Mustafa Ertugrul Oner , Arda Kamil Bafra , Levent Yakay
发明人： Mustafa Ertugrul Oner , Arda Kamil Bafra , Levent Yakay
IPC分类号： H03D3/24
CPC分类号： H03L7/087 , H03L7/089 , H03L7/146
摘要： An apparatus that includes a module for controlling the frequency of a voltage controlled oscillator (VCO) as part of a phase locked loop (PLL), or clock and data recovery (CDR) when an input reference signal to the PLL or serial data to the CDR has ceased from being received. In particular, the apparatus comprises a VCO adapted to generate a VCO clock signal, a first control module adapted to control the frequency of the VCO clock signal based on the input reference signal, and a second control module adapted to control the frequency of the VCO clock signal in response to an absence of the input reference signal. By controlling the frequency of the VCO clock signal during an absence of the input reference signal, the first control module is able to more easily re-acquire control the frequency of the VCO clock signal when the input reference signal is received again.
摘要翻译：一种装置，其包括用于控制作为锁相环（PLL）的一部分的压控振荡器（VCO）的频率的模块，或者当输入到PLL的参考信号或到串行数据的时钟和数据恢复（CDR）时， CDR已停止接收。具体地，该装置包括适于产生VCO时钟信号的VCO，适于基于输入参考信号来控制VCO时钟信号的频率的第一控制模块，以及适于控制VCO的频率的第二控制模块响应于不存在输入参考信号的时钟信号。通过在没有输入参考信号的情况下控制VCO时钟信号的频率，当再次接收输入参考信号时，第一控制模块能够更容易地重新获取控制VCO时钟信号的频率。

58. 发明授权

US08090335B1 Method and apparatus for an adaptive step frequency calibration 有权
标题翻译：自适应步进频率校准的方法和装置
公开(公告)号：US08090335B1
公开(公告)日：2012-01-03
申请号：US11484192
申请日：2006-07-11
申请人： Khaldoun Bataineh
发明人： Khaldoun Bataineh
IPC分类号： H03J7/32 , H04B1/06 , H04B7/00 , H03L7/06 , H03L7/00 , H03D3/24 , G06F1/00
CPC分类号： H03L7/10 , H03L7/089
摘要： An open loop frequency calibration algorithm is employed whereby frequency counters are utilized to provide frequency information concerning the difference in frequency between a local oscillator and a reference signal prior to obtaining phase locked operation of a phase locked loop (PLL). The frequency difference is then used to adjust the local oscillator's frequency to be changed by a value that is proportional to the frequency difference measured. Through adaptive calibration of the local oscillator's frequency prior to closed loop PLL operations, a substantial reduction in the amount of time required to obtain phase/frequency coherent operation of the PLL is realized.
摘要翻译：使用开环频率校准算法，其中利用频率计数器在获得锁相环（PLL）的锁相操作之前提供关于本地振荡器和参考信号之间的频率差的频率信息。然后使用频率差来调整本地振荡器的频率，以改变与测量的频差成比例的值。通过在闭环PLL操作之前对本地振荡器的频率进行自适应校准，实现了获得PLL的相位/频率相干操作所需的时间量的显着减少。

59. 发明申请

US20110234275A1 PLL CIRCUIT 有权
标题翻译： PLL电路
公开(公告)号：US20110234275A1
公开(公告)日：2011-09-29
申请号：US13028815
申请日：2011-02-16
申请人： Hajime SATO
发明人： Hajime SATO
IPC分类号： H03L7/08
CPC分类号： H03L7/0895 , H03L7/089 , H03L7/10
摘要： In the PLL circuit including a phase comparator, a charge pump circuit, a loop filter, and a voltage controlled oscillator, the loop band after the locking can be expanded in such a manner that, when the phase difference between a reference clock signal and a feedback clock signal is larger than a threshold value, an output current corresponding to the phase difference is outputted by reducing the change of the output current per unit amount of the phase difference, and that, when the phase difference is at most the threshold value, the output current corresponding to the phase difference is outputted by increasing the change of the output current per unit amount of the phase difference.
摘要翻译：在包括相位比较器，电荷泵电路，环路滤波器和压控振荡器的PLL电路中，锁定之后的环带可以以这样的方式扩展，即当参考时钟信号和反馈时钟信号大于阈值时，通过减少每单位量相位差的输出电流的变化来输出与相位差相对应的输出电流，并且当相位差至多为阈值时，通过增加每单位量相位差的输出电流的变化来输出与相位差对应的输出电流。

60. 发明申请

US20110228616A1 Clock Generator Circuits with Non-Volatile Memory for Storing and/or Feedback-Controlling Phase and Frequency 有权
标题翻译：具有用于存储和/或反馈控制相位和频率的非易失性存储器的时钟发生器电路
公开(公告)号：US20110228616A1
公开(公告)日：2011-09-22
申请号：US12674598
申请日：2008-08-22
申请人： Jaeha Kim , Brent Haukness
发明人： Jaeha Kim , Brent Haukness
IPC分类号： G11C8/18 , G11C7/00
CPC分类号： H03L7/187 , H03L7/0812 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/10 , H03L2207/08
摘要： A clock-signal generator (e.g. a PLL or a DLL) uses non-volatile memory to store an analog control voltage that determines an output phase and/or frequency of the clock-signal generator. Locked loops take time to lock on a given reference frequency. To keep this time to a minimum, NVM 105 stores the control voltage during periods of inactivity, such as when the signal generator is powered down or in a standby mode. Non-volatile memory stores control voltages during operation in other embodiments to relax the area requirements otherwise required for integration capacitors to store phase and frequency information.
摘要翻译：时钟信号发生器（例如PLL或DLL）使用非易失性存储器来存储确定时钟信号发生器的输出相位和/或频率的模拟控制电压。锁定环路需要时间来锁定给定的参考频率。为了将此时间保持在最低限度，NVM105在不活动期间存储控制电压，例如当信号发生器断电或处于待机模式时。非易失性存储器在其他实施例中在操作期间存储控制电压，以放松否则为积分电容器存储相位和频率信息所需的面积要求。

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