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1. 发明授权

US5745315A Phase error detector and magnetic storage device using the same 失效
标题翻译：相位误差检测器和使用其的磁存储器件
公开(公告)号：US5745315A
公开(公告)日：1998-04-28
申请号：US742484
申请日：1996-11-01
申请人： Morishige Aoyama
发明人： Morishige Aoyama
IPC分类号： G11B20/14 , G11B5/09 , G11B19/04 , G11B20/10 , G11B20/18
CPC分类号： G11B19/04 , G11B20/10009 , G11B5/09
摘要： In the PRML, the probability of false locking of phase in a metastable state is reduced and the residual phase error between a readout signal and a clock signal used in an A/D conversion is eliminated by a phase detector (10) which comprises a level decision circuit 12 for determining one of a plurality of aimed equalization levels predetermined in the partial response signalling system which is the closest to a sampled value of an equalized waveform equalized substantially to the waveform of the partial response signalling system, a waveform gradient judge circuit (14) for determining a gradient of the equalized waveform on the basis of the aimed equalization level determined by the level decision circuit (12), an equalization error calculation circuit (16) for calculating an equalization error which is a difference between the sampled value of the equalized waveform and the aimed equalization level determined by the level decision circuit (12) and a phase error calculation circuit (18) for detecting a phase error on the basis of the equalization error calculated by the equalization error calculation circuit (16) and the gradient of the equalized waveform determined by the waveform gradient judge circuit (14).
摘要翻译：在PRML中，相位在亚稳态的假锁定的概率降低，并且在A / D转换中使用的读出信号和时钟信号之间的残留相位误差被相位检测器（10）消除，该相位检测器（10）包括一个电平决定电路12，用于确定部分响应信号系统中预定的多个目标均衡电平中的一个，其最接近基本上等于部分响应信号系统的波形的均衡波形的采样值;波形梯度判断电路 14），用于基于由电平判定电路（12）确定的目标均衡电平来确定均衡波形的梯度;均衡误差计算电路（16），用于计算均衡误差，该均衡误差是采样值均衡波形和由电平判定电路（12）确定的目标均衡电平和相位误差计算电路（1） 8），用于基于由均衡误差计算电路（16）计算的均衡误差和由波形梯度判断电路（14）确定的均衡波形的梯度来检测相位误差。

2. 发明授权

US07336754B2 Clock and data recovery circuit 有权
标题翻译：时钟和数据恢复电路
公开(公告)号：US07336754B2
公开(公告)日：2008-02-26
申请号：US10861355
申请日：2004-06-07
申请人： Morishige Aoyama
发明人： Morishige Aoyama
IPC分类号： H03D3/24
CPC分类号： H03D13/004 , H03L7/0814 , H03L7/093 , H03L7/107 , H04L7/0025 , H04L7/0337
摘要： A clock and data recovery circuit, for tracking frequency-modulated input data, comprises a phase detector for receiving a data signal and a synchronous clock signal, detecting a phase delay or a phase advance, and outputting an UP1/DOWN1 signal, first and second integrators for integrating the UP1/DOWN1 signal and outputting an UP2/DOWN2 signal and an UP3/DOWN3 signal, respectively, a pattern generator for receiving the UP3/DOWN3 signal from the second integrator to output an UP4/DOWN4 signal, a mixer for receiving the UP2/DOWN2 signal from the first integrator and the UP4/DOWN4 signal from the pattern generator and generating an UP5/DOWN5 signal for output, and a phase interpolator for interpolating the phase of an input clock signal based on the UP5/DOWN5 signal from the mixer, for output are provided. A clock signal output from the interpolator is fed back to the phase detector as the clock.
摘要翻译：用于跟踪频率调制输入数据的时钟和数据恢复电路包括用于接收数据信号和同步时钟信号的相位检测器，检测相位延迟或相位提前，并且先输出UP 1 / DOWN 1信号以及用于对UP 1 / DOWN 1信号进行积分并分别输出UP 2 / DOWN 2信号和UP 3 / DOWN 3信号的第二积分器，用于从第二积分器接收UP 3 / DOWN 3信号的模式发生器输出 UP 4 / DOWN 4信号，用于从第一积分器接收UP 2 / DOWN 2信号的混合器和来自模式发生器的UP 4 / DOWN 4信号并产生用于输出的UP 5 / DOWN 5信号，以及相位提供了用于根据来自混频器的UP 5 / DOWN 5信号内插输入时钟信号的相位的内插器，用于输出。从内插器输出的时钟信号作为时钟反馈到相位检测器。

3. 发明申请

US20120049910A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20120049910A1
公开(公告)日：2012-03-01
申请号：US13137144
申请日：2011-07-22
申请人： Morishige Aoyama
发明人： Morishige Aoyama
IPC分类号： H03L7/08
CPC分类号： H03L7/089
摘要： A semiconductor device includes a clock-and-data recovery circuit including a phase tracking loop that generates a phase difference signal indicating a phase difference between a reception clock generated from a transmission clock and an input signal and makes the reception clock track the input signal, a frequency tracking loop that performs control to make a frequency of the reception clock track a frequency of the input signal, the clock-and-data recovery circuit being configured to extract a data signal and a synchronization clock from the input signal and to control a phase and a frequency of the reception clock, a frequency error adjuster that increases or decreases a value indicated by a frequency adjustment signal according to a frequency difference signal generated based on the phase difference signal, and an oscillator that increases or decreases a frequency of the transmission clock based on the frequency adjustment signal.
摘要翻译：半导体器件包括时钟和数据恢复电路，其包括相位跟踪环路，该相位跟踪环路产生指示从传输时钟产生的接收时钟与输入信号之间的相位差的相位差信号，并使接收时钟跟踪输入信号，执行控制以使接收时钟的频率跟踪输入信号的频率的频率跟踪环路，所述时钟和数据恢复电路被配置为从输入信号提取数据信号和同步时钟，并且控制相位和接收时钟的频率，频率误差调整器，其根据基于相位差信号产生的频差信号增加或减少由频率调整信号指示的值;以及振荡器，其增加或减少接收时钟的频率传输时钟基于频率调整信号。

4. 发明申请

US20080253494A1 Clock and data recovery circuit 失效
标题翻译：时钟和数据恢复电路
公开(公告)号：US20080253494A1
公开(公告)日：2008-10-16
申请号：US12081102
申请日：2008-04-10
申请人： Morishige Aoyama
发明人： Morishige Aoyama
IPC分类号： H04L7/00
CPC分类号： H03L7/089 , H03L7/0814 , H03L7/093 , H04L7/0025 , H04L7/0337
摘要： The phase detector compares the phase of a synchronous clock signal from the clock interpolator with the phase of serial data and outputs a phase error signal corresponding to a comparison result. The first integrator performs integration of the phase error signal and obtains a phase correction control signal for tracking phase shift of the serial data. The second integrator further performs integration of the phase correction control signal and obtains an up/down signal. The pattern generator generates a frequency correction control signal for tracking frequency shift of the serial data from the up/down signal. The product of the pattern length of the pattern generator and the count width of the second integrator is equal to or larger than a threshold that becomes larger as the count width of the first integrator is larger.
摘要翻译：相位检测器将来自时钟插入器的同步时钟信号的相位与串行数据的相位进行比较，并输出与比较结果相对应的相位误差信号。第一个积分器执行相位误差信号的积分，并获得用于跟踪串行数据的相移的相位校正控制信号。第二积分器进一步执行相位校正控制信号的积分并获得上/下信号。模式发生器产生用于跟踪来自上/下信号的串行数据的频移的频率校正控制信号。图案发生器的图案长度和第二积分器的计数宽度的乘积等于或大于随着第一积分器的计数宽度变大而变大的阈值。

5. 发明授权

US08781054B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08781054B2
公开(公告)日：2014-07-15
申请号：US13137144
申请日：2011-07-22
申请人： Morishige Aoyama
发明人： Morishige Aoyama
IPC分类号： H03D3/24
CPC分类号： H03L7/089
摘要： A semiconductor device includes a clock-and-data recovery circuit including a phase tracking loop that generates a phase difference signal indicating a phase difference between a reception clock generated from a transmission clock and an input signal and makes the reception clock track the input signal, a frequency tracking loop that performs control to make a frequency of the reception clock track a frequency of the input signal, the clock-and-data recovery circuit being configured to extract a data signal and a synchronization clock from the input signal and to control a phase and a frequency of the reception clock, a frequency error adjuster that increases or decreases a value indicated by a frequency adjustment signal according to a frequency difference signal generated based on the phase difference signal, and an oscillator that increases or decreases a frequency of the transmission clock based on the frequency adjustment signal.
摘要翻译：半导体器件包括时钟和数据恢复电路，其包括相位跟踪环路，该相位跟踪环路产生指示从传输时钟产生的接收时钟与输入信号之间的相位差的相位差信号，并使接收时钟跟踪输入信号，执行控制以使接收时钟的频率跟踪输入信号的频率的频率跟踪环路，所述时钟和数据恢复电路被配置为从输入信号提取数据信号和同步时钟，并且控制相位和接收时钟的频率，频率误差调整器，其根据基于相位差信号产生的频差信号增加或减少由频率调整信号指示的值;以及振荡器，其增加或减少接收时钟的频率传输时钟基于频率调整信号。

6. 发明授权

US08199868B2 Clock and data recovery circuit 失效
标题翻译：时钟和数据恢复电路
公开(公告)号：US08199868B2
公开(公告)日：2012-06-12
申请号：US12081102
申请日：2008-04-10
申请人： Morishige Aoyama
发明人： Morishige Aoyama
IPC分类号： H03D3/24
CPC分类号： H03L7/089 , H03L7/0814 , H03L7/093 , H04L7/0025 , H04L7/0337
摘要： The phase detector compares the phase of a synchronous clock signal from the clock interpolator with the phase of serial data and outputs a phase error signal corresponding to a comparison result. The first integrator performs integration of the phase error signal and obtains a phase correction control signal for tracking phase shift of the serial data. The second integrator further performs integration of the phase correction control signal and obtains an up/down signal. The pattern generator generates a frequency correction control signal for tracking frequency shift of the serial data from the up/down signal. The product of the pattern length of the pattern generator and the count width of the second integrator is equal to or larger than a threshold that becomes larger as the count width of the first integrator is larger.
摘要翻译：相位检测器将来自时钟插入器的同步时钟信号的相位与串行数据的相位进行比较，并输出与比较结果相对应的相位误差信号。第一个积分器执行相位误差信号的积分，并获得用于跟踪串行数据的相移的相位校正控制信号。第二积分器进一步执行相位校正控制信号的积分并获得上/下信号。模式发生器产生用于跟踪来自上/下信号的串行数据的频移的频率校正控制信号。图案发生器的图案长度和第二积分器的计数宽度的乘积等于或大于随着第一积分器的计数宽度变大而变大的阈值。

7. 发明授权

US08036318B2 Clock and data recovery circuit 失效
标题翻译：时钟和数据恢复电路
公开(公告)号：US08036318B2
公开(公告)日：2011-10-11
申请号：US12078934
申请日：2008-04-08
申请人： Morishige Aoyama
发明人： Morishige Aoyama
IPC分类号： H04L27/00
CPC分类号： H03L7/0814 , H03L7/085 , H04L7/0025 , H04L7/0337
摘要： The phase detector compares the phases of a synchronous clock signal and serial data and outputs a phase error signal corresponding to a comparison result. The second integrator performs integration of the phase error signal to obtain a phase correction control signal for tracking phase shift of the serial data. The first integrator performs integration of the phase error signal in each smoothing period with a predetermined length to obtain a smoothed error signal. The pattern generator generates a pattern for changing the phase of the synchronous clock signal at a frequency corresponding to the smoothed error signal in each pattern generation period with a predetermined length and outputs the pattern as a frequency correction control signal. The first integrator receives the frequency correction control signal which is fed back and changes the length of the smoothing period according to the direction of a change in the frequency of generating the frequency correction control signal.
摘要翻译：相位检测器比较同步时钟信号和串行数据的相位，并输出与比较结果相对应的相位误差信号。第二积分器执行相位误差信号的积分以获得用于跟踪串行数据的相移的相位校正控制信号。第一积分器在每个平滑周期中执行预定长度的相位误差信号的积分，以获得平滑的误差信号。图案生成器生成用于以预定长度在每个图案生成周期中以与平滑的误差信号相对应的频率改变同步时钟信号的相位的模式，并将该模式作为频率校正控制信号输出。第一积分器接收反馈的频率校正控制信号，并根据产生频率校正控制信号的频率变化的方向改变平滑周期的长度。

8. 发明申请

US20080253493A1 Clock and data recovery circuit 失效
标题翻译：时钟和数据恢复电路
公开(公告)号：US20080253493A1
公开(公告)日：2008-10-16
申请号：US12078934
申请日：2008-04-08
申请人： Morishige Aoyama
发明人： Morishige Aoyama
IPC分类号： H04L7/00
CPC分类号： H03L7/0814 , H03L7/085 , H04L7/0025 , H04L7/0337
摘要： The phase detector compares the phases of a synchronous clock signal and serial data and outputs a phase error signal corresponding to a comparison result. The second integrator performs integration of the phase error signal to obtain a phase correction control signal for tracking phase shift of the serial data. The first integrator performs integration of the phase error signal in each smoothing period with a predetermined length to obtain a smoothed error signal. The pattern generator generates a pattern for changing the phase of the synchronous clock signal at a frequency corresponding to the smoothed error signal in each pattern generation period with a predetermined length and outputs the pattern as a frequency correction control signal. The first integrator receives the frequency correction control signal which is fed back and changes the length of the smoothing period according to the direction of a change in the frequency of generating the frequency correction control signal.
摘要翻译：相位检测器比较同步时钟信号和串行数据的相位，并输出与比较结果相对应的相位误差信号。第二积分器执行相位误差信号的积分以获得用于跟踪串行数据的相移的相位校正控制信号。第一积分器在每个平滑周期中执行预定长度的相位误差信号的积分，以获得平滑的误差信号。图案生成器生成用于以预定长度在每个图案生成周期中以与平滑的误差信号相对应的频率改变同步时钟信号的相位的模式，并将该模式作为频率校正控制信号输出。第一积分器接收反馈的频率校正控制信号，并根据产生频率校正控制信号的频率变化的方向改变平滑周期的长度。

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