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1. 发明授权

US07742553B1 VCO initial frequency calibration circuit and method therefore 有权
标题翻译： VCO初始频率校准电路和方法因此
公开(公告)号：US07742553B1
公开(公告)日：2010-06-22
申请号：US11035773
申请日：2005-01-14
申请人： Khaldoun Bataineh , Michael Mass , Michael J. Gaboury , David E. Tetzlaff
发明人： Khaldoun Bataineh , Michael Mass , Michael J. Gaboury , David E. Tetzlaff
IPC分类号： H03D3/24
CPC分类号： H03C3/0991 , H03L7/087 , H03L7/099 , H03L7/113 , H03L2207/06
摘要： A device and a method for processing high data rate serial data includes a VCO initial frequency calibration circuit. The circuit includes a frequency detection block for indicating a difference between a reference clock and a divided VCO clock, a frequency calibration block that produces a digital output signal based upon the difference between the reference clock and the divided VCO clock, and a digital-to-analog converter for producing an analog VCO adjust signal. The frequency detection block produces a plurality of signals based upon the reference clock and the divided VCO clock. A plurality of user selected inputs selects a frequency detection lock range and hysteresis range and a coarse loop open calibration lock and hysteresis range. The frequency calibration block implements a state machine for producing the digital output signal that sets the initial operating frequency then adjusts the frequency of the VCO clock.
摘要翻译：用于处理高数据速率串行数据的设备和方法包括VCO初始频率校准电路。电路包括用于指示参考时钟和分频VCO时钟之间的差的频率检测块，基于参考时钟和分频VCO时钟之间的差产生数字输出信号的频率校准块，以及数字到 -analog转换器，用于产生模拟VCO调整信号。频率检测块基于参考时钟和分频VCO时钟产生多个信号。多个用户选择的输入选择频率检测锁定范围和滞后范围以及粗循环打开校准锁定和滞后范围。频率校准块实现了用于产生数字输出信号的状态机，其设置初始操作频率，然后调节VCO时钟的频率。

2. 发明授权

US07532645B1 Receiver operable to receive data at a lower data rate 有权
标题翻译：接收器可操作以以较低的数据速率接收数据
公开(公告)号：US07532645B1
公开(公告)日：2009-05-12
申请号：US11035613
申请日：2005-01-14
申请人： Khaldoun Bataineh , Stephen D. Anderson , Michael Maas , David E. Tetzlaff
发明人： Khaldoun Bataineh , Stephen D. Anderson , Michael Maas , David E. Tetzlaff
IPC分类号： H04J3/07
CPC分类号： H04L7/0338
摘要： A receiver that includes: an oversampling module that converts a serial stream of data into a plurality of streams of oversampled data based on the receive clock; a transition location module that determines transition locations of the streams of oversampled data and the receive clock; a pointer adjust module that determines a pointer variable based on the transition locations and the receive clock; a data selection module that determines an equivalent data value for the streams of oversampled data based on the pointer variable; a staging register module that produces an offset data word and an extra data word from the equivalent data value for the oversampled data streams; and a output register module that produces a parallel data output from at least one of the offset data word and the extra data word.
摘要翻译：一种接收机，包括：过采样模块，其基于所述接收时钟将串行数据流转换为多个过采样数据流; 转移位置模块，其确定过采样数据流和接收时钟的转换位置; 指针调整模块，其基于所述转换位置和所述接收时钟来确定指针变量; 数据选择模块，其基于指针变量确定过采样数据流的等效数据值; 分级寄存器模块，用于从过采样数据流的等效数据值产生偏移数据字和额外的数据字; 以及输出寄存器模块，其从偏移数据字和额外数据字中的至少一个产生并行数据输出。

3. 发明授权

US07761776B1 Method and apparatus for a modular, programmable cyclic redundancy check design 有权
标题翻译：用于模块化可编程循环冗余校验设计的方法和装置
公开(公告)号：US07761776B1
公开(公告)日：2010-07-20
申请号：US11265815
申请日：2005-11-03
申请人： Khaldoun Bataineh
发明人： Khaldoun Bataineh
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/6516
摘要： A linear feedback shift register (LFSR) based design is applied to cyclic redundancy check (CRC) modules, in which a CRC building block having a minimum width is implemented. The CRC building block accepts a generator polynomial as an input design parameter to build a CRC block module. The modularity of the design then allows a larger CRC block design to be constructed from multiple CRC block modules such that wider data width blocks may be accommodated. The LFSR based designs are extended to communication systems that may require scrambling and descrambling functionality.
摘要翻译：基于线性反馈移位寄存器（LFSR）的设计被应用于循环冗余校验（CRC）模块，其中实现了具有最小宽度的CRC构建块。 CRC构建块接受生成多项式作为输入设计参数来构建CRC块模块。因此，设计的模块化允许由多个CRC块模块构建更大的CRC块设计，使得可以容纳更宽的数据宽度块。基于LFSR的设计扩展到可能需要加扰和解扰功能的通信系统。

4. 发明授权

US07363573B1 Method and apparatus for a dedicated cyclic redundancy check block within a device 有权
标题翻译：用于设备内的专用循环冗余校验块的方法和装置
公开(公告)号：US07363573B1
公开(公告)日：2008-04-22
申请号：US11032396
申请日：2005-01-10
申请人： Khaldoun Bataineh
发明人： Khaldoun Bataineh
IPC分类号： H03M13/00
CPC分类号： H03M13/09 , H03M13/6516
摘要： A dedicated Cyclic Redundancy Check (CRC) block within an Integrated circuit IC), for example, a Programmable Logic Device (PLD), allows direct access to the CRC block from within the programmable logic of the IC. Accessibility to the CRC block is achieved from any communication layer of the fabric due to the separation of the CRC block from the physical layer. All inputs and outputs of the CRC block are provided to the fabric to allow full controllability of CRC operation including data width, initial CRC value, and idle cycle introduction.
摘要翻译：集成电路IC内的专用循环冗余校验（CRC）块，例如可编程逻辑器件（PLD））允许从IC的可编程逻辑内直接访问CRC块。由于CRC块与物理层的分离，可以从结构的任何通信层实现对CRC块的可访问性。将CRC块的所有输入和输出提供给结构，以允许CRC操作的完全可控性，包括数据宽度，初始CRC值和空闲周期引入。

5. 发明授权

US08090335B1 Method and apparatus for an adaptive step frequency calibration 有权
标题翻译：自适应步进频率校准的方法和装置
公开(公告)号：US08090335B1
公开(公告)日：2012-01-03
申请号：US11484192
申请日：2006-07-11
申请人： Khaldoun Bataineh
发明人： Khaldoun Bataineh
IPC分类号： H03J7/32 , H04B1/06 , H04B7/00 , H03L7/06 , H03L7/00 , H03D3/24 , G06F1/00
CPC分类号： H03L7/10 , H03L7/089
摘要： An open loop frequency calibration algorithm is employed whereby frequency counters are utilized to provide frequency information concerning the difference in frequency between a local oscillator and a reference signal prior to obtaining phase locked operation of a phase locked loop (PLL). The frequency difference is then used to adjust the local oscillator's frequency to be changed by a value that is proportional to the frequency difference measured. Through adaptive calibration of the local oscillator's frequency prior to closed loop PLL operations, a substantial reduction in the amount of time required to obtain phase/frequency coherent operation of the PLL is realized.
摘要翻译：使用开环频率校准算法，其中利用频率计数器在获得锁相环（PLL）的锁相操作之前提供关于本地振荡器和参考信号之间的频率差的频率信息。然后使用频率差来调整本地振荡器的频率，以改变与测量的频差成比例的值。通过在闭环PLL操作之前对本地振荡器的频率进行自适应校准，实现了获得PLL的相位/频率相干操作所需的时间量的显着减少。

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