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    • 51. 发明授权
    • Electronic circuitry
    • 电子电路
    • US06556089B2
    • 2003-04-29
    • US09529076
    • 2000-04-06
    • John Wood
    • John Wood
    • H03B518
    • H03B5/1852G06F1/10H03K3/03H03K3/86H03L7/00
    • Timing signal generation and distribution are combined in operation of a signal path exhibiting endless electromagnetic continuity affording signal phase inversion and having associated regenerative active means. Two-or more-phases of substantially square-wave bipolar signals arise directly in travelling wave transmission-line embodiments compatible with semiconductor fabrication including CMOS. Coordination by attainable frequency synchronism with phase coherence for several such oscillating signal paths has intra-IC inter-IC and printed circuit board impact.
    • 定时信号产生和分配被组合在具有提供信号相位反转的无止境电磁连续性并且具有相关联的再生有源装置的信号路径的操作中。 基本方波双极性信号的两相或更多相直接出现在与包括CMOS的半导体制造兼容的行波传输线实施例中。 通过实现具有相位相干性的几个这样的振荡信号路径的可实现的频率同步的协调具有IC内IC和印刷电路板的影响。
    • 52. 发明授权
    • Clock distribution network with dual wire routing
    • 时钟分配网络,双线路
    • US6144224A
    • 2000-11-07
    • US348041
    • 1999-07-06
    • Jin-Fuw LeeDaniel Lawrence Ostapko
    • Jin-Fuw LeeDaniel Lawrence Ostapko
    • G06F1/10H03K3/86H03K19/00
    • G06F1/10H03K3/86
    • A new clock distribution network design for VLSI circuits which effectively reduces skew without the area and power penalty associated with prior clock designs. Two wires emanating from the clock in opposite directions or, alternatively, two wires connected in series and running parallel, are used to route clock signals from the clock source to the next routing segment. The next routing segment routes clock signals to the tapping point near the circuit component by two emanated wires from the previous routing segment. Clock signals from the routing segments are fed through two-input NOR gates (alternatively, two-input NAND gates) to the clock pins. The clock signal arrival time is roughly equal to the simultaneous switching gate delay plus the average arrival times from the two paths, which turns out approximately the same across different tapping points, thus minimizing clock skews. Narrow wires may be used for routing, resulting in moderate power consumption.
    • 一种用于VLSI电路的新型时钟分配网络设计,可有效减少偏移,而无需与现有时钟设计相关的面积和功耗。 使用从时钟相反方向发出的两根线,或者两根并联连接并联并联的两条线,将时钟信号从时钟源路由到下一个路由段。 下一个路由段将时钟信号通过来自先前路由段的两条发射线路将时钟信号路由到电路组件附近的分接点。 来自路由段的时钟信号通过双输入NOR门(或者两个输入NAND门)馈送到时钟引脚。 时钟信号到达时间大致等于同时切换门延迟加上两条路径的平均到达时间,这两条路径的平均到达时间在不同的分接点之间大致相同,从而最小化时钟偏移。 窄导线可用于布线,导致中等功耗。
    • 56. 发明授权
    • Programmable delay line oscillator
    • 可编程延迟线振荡器
    • US4197506A
    • 1980-04-08
    • US919158
    • 1978-06-26
    • Merle J. Fogelstrom
    • Merle J. Fogelstrom
    • H03K3/86H03K1/16H03K1/18
    • H03K3/86
    • An electronically programmable oscillator has a plurality of digitally incremented selectable frequency signal outputs, providing a wide range of incrementally distinguishable, selectable frequencies having defined pulse widths. Incremental frequency selection is made through delay lines and bypassable interpolating delay lines connected in series. Selectable bypassable delay loops can be inserted into the oscillator signal path by manually controlled electronic, programmable selections. The width and shape of the pulse is regulated at several stages of the circuit, using solid state electronic components.
    • 电子可编程振荡器具有多个数字递增的可选择频率信号输出,提供具有定义的脉冲宽度的宽范围的递增可区分的可选频率。 通过延迟线和可连接的内插延迟线进行增量选择。 可选择的可旁路延迟环可以通过手动控制的电子,可编程选择插入振荡器信号路径。 使用固态电子元件在电路的几个阶段调节脉冲的宽度和形状。