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1. 发明公开

US20240237435A1 Semiconductor Device, Display Apparatus, and Electronic Device 审中-公开
公开(公告)号：US20240237435A1
公开(公告)日：2024-07-11
申请号：US18288495
申请日：2022-04-20
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Kazuki TSUDA , Hidefumi RIKIMARU , Satoru OHSHITA , Hiromichi GODO , Yoshiyuki KUROKAWA
IPC分类号： H10K59/131
CPC分类号： H10K59/131
摘要： A semiconductor device with reduced circuit area is provided. The semiconductor device includes first and second cell arrays and a first converter circuit. The first cell array includes a first cell and a second cell in the same row, and the second cell array includes third and fourth cells in the same row. The first cell is electrically connected to first and second wirings, the second cell is electrically connected to the first and third wirings, the third cell is electrically connected to fourth and sixth wirings, and the fourth cell is electrically connected to fifth and seventh wirings. The sixth wiring is electrically connected to the seventh wiring. The first to fourth cells each have a function of outputting current corresponding to a product of retained data and input data. Specifically, the first cell, the second cell, the third cell, and the fourth cell output current to the second wiring, the third wiring, the sixth wiring, and the seventh wiring, respectively. The first converter circuit has a function of making data corresponding to a total amount of current flowing through the second and third wirings flow to the fourth and fifth wirings, respectively.

2. 发明公开

US20240143441A1 OPERATION METHOD OF SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20240143441A1
公开(公告)日：2024-05-02
申请号：US18382077
申请日：2023-10-20
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Hidefumi RIKIMARU , Seiko INOUE , Hiromichi GODO , Yoshiyuki KUROKAWA
IPC分类号： G06F11/10 , G06F7/544 , G06F11/07
CPC分类号： G06F11/1068 , G06F7/5443 , G06F11/076
摘要： To provide an operation method of a semiconductor device in which a variation in arithmetic operation results is reduced. The semiconductor device includes first and second cell arrays and first to fifth circuits. First, third standard data is written from the fourth circuit to the second cell array, and first standard data is written from the first circuit to the first cell array. Then, second standard data is transmitted from the second circuit to the first cell array, a result of a product-sum operation of the first standard data and the second standard data is input from the first cell array to the third circuit, and fourth standard data corresponding to the result of the product-sum operation is transmitted from the third circuit to the second cell array. A result of a product-sum operation of the third standard data and the fourth standard data is input from the second cell array to the fifth circuit, and an output value corresponding to the result of the product-sum operation is output from the fifth circuit. Correction data corresponding to the difference between the output value and an expected value is retained in an empty cell of the first cell array and correction coefficients of the first and second cell arrays are calculated.

3. 发明公开

US20240134605A1 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 审中-公开
公开(公告)号：US20240134605A1
公开(公告)日：2024-04-25
申请号：US18278451
申请日：2022-02-24
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Yoshiyuki KUROKAWA , Hiromichi GODO , Kazuki TSUDA , Satoru OHSHITA , Hidefumi RIKIMARU
IPC分类号： G06F7/523 , G06F7/50 , G09G3/3208 , G11C11/405 , H10B12/00 , H10K59/121
CPC分类号： G06F7/523 , G06F7/50 , G09G3/3208 , G11C11/405 , H10B12/00 , H10K59/1213 , H10K59/1216
摘要： A semiconductor device with a novel structure is provided. The semiconductor device includes a cell array performing a product-sum operation of a first layer and a product-sum operation of a second layer in an artificial neural network, a first circuit from which first data is input to the cell array, and a second circuit to which second data is output from the cell array. The cell array includes a plurality of cells. The cell array includes a first region and a second region. In a first period, the first region is supplied with the t-th (t is a natural number greater than or equal to 2) first data from the first circuit and outputs the t-th second data according to the product-sum operation of the first layer to the second circuit. In the first period, the second region is supplied with the (t+1)-th first data from the first circuit and outputs the (t+1)-th second data according to the product-sum operation of the second layer to the first circuit.

4. 发明公开

US20230369329A1 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 审中-公开
公开(公告)号：US20230369329A1
公开(公告)日：2023-11-16
申请号：US18142740
申请日：2023-05-03
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yoshiyuki KUROKAWA , Satoru OHSHITA , Hidefumi RIKIMARU
IPC分类号： H01L27/092 , H03M1/72
CPC分类号： H01L27/092 , H03M1/72
摘要： A semiconductor device with low power consumption is provided. The semiconductor device includes a first layer and a second layer. The first layer includes a first cell and a first to a third circuit, and the second layer includes a second cell and a fourth and a fifth circuit. The first, second, and fourth circuits each have a function of converting digital data into analog current. The first cell calculates a product of a value from the first current and a value from the second circuit and inputs a calculation result into a third circuit as current. The third circuit generates analog current from the input current. The second cell calculates a product of a value from the third circuit and a value from the fourth circuit and inputs a calculation result into the fifth circuit as current. The fifth circuit generates analog current from the input current.

5. 发明申请

US20220124275A1 DRIVING METHOD OF SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 有权
公开(公告)号：US20220124275A1
公开(公告)日：2022-04-21
申请号：US17567234
申请日：2022-01-03
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yoshiyuki KUROKAWA
IPC分类号： H04N5/3745 , H01L27/146 , G01S7/481 , G01S7/4863 , H04N5/343 , H04N5/347 , G01S17/894 , G01S17/89 , G01S17/02
摘要： A driving method of a semiconductor device that takes three-dimensional images with short duration is provided. In a first step, a light source starts to emit light, and first potential corresponding to the total amount of light received by a first photoelectric conversion element and a second photoelectric conversion element is written to a first charge accumulation region. In a second step, the light source stops emitting light and second potential corresponding to the total amount of light received by the first photoelectric conversion element and the second photoelectric conversion element is written to a second charge accumulation region. In a third step, first data corresponding to the potential written to the first charge accumulation region is read. In a fourth step, second data corresponding to the potential written to the second charge accumulation region is read.

6. 发明申请

US20210233460A1 SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE 有权
公开(公告)号：US20210233460A1
公开(公告)日：2021-07-29
申请号：US17227702
申请日：2021-04-12
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yoshiyuki KUROKAWA
IPC分类号： G09G3/20 , H01L27/12 , H01L29/786 , G02F1/1335 , G06F1/3218 , G06F1/3234
摘要： An object is to provide a semiconductor device with low power consumption. The semiconductor device includes a controller, a register, and an image processing portion. The image processing portion has a function of taking image data from a frame memory and a parameter from the register and processing the image data by using the parameter. The frame memory has a function of retaining the image data while power supply is stopped. The register has a function of retaining the parameter while power supply is stopped. The controller controls power supply to the register, the frame memory, and the image processing portion. The register includes first and second scan chain registers. The first scan chain register stores a parameter related to a first display region. The second scan chain register stores a parameter related to a second display region. A parameter is changed by loading of data of the first or second scan chain register.

7. 发明申请

US20210142836A1 SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE 有权
公开(公告)号：US20210142836A1
公开(公告)日：2021-05-13
申请号：US16617919
申请日：2018-06-07
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yoshiyuki KUROKAWA , Shunpei YAMAZAKI
IPC分类号： G11C11/16 , G06F9/4401 , H01L27/108 , G11C11/402 , G11C5/14 , G06F21/57
摘要： The operation speed of a semiconductor device is improved.
The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.

8. 发明申请

US20200349898A1 DISPLAY DEVICE AND ELECTRONIC DEVICE 审中-公开
公开(公告)号：US20200349898A1
公开(公告)日：2020-11-05
申请号：US16931793
申请日：2020-07-17
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yoshiyuki KUROKAWA
IPC分类号： G09G3/36 , G09G3/3233
摘要： A display device that performs image correction in accordance with external light environment is provided. The display device includes a host device and an optical sensor. In addition, the display device includes a processing circuit. The host device has a function of performing arithmetic processing using a neural network on software and a function of performing supervised learning with the neural network. The processing circuit has a function of performing arithmetic processing using a neural network on hardware. The optical sensor has a function of obtaining illuminance of external light. The obtained illuminance of external light is inputted to the host device, and a luminance and color tone preferred by users are regarded as teacher data, whereby learning is performed on the neural network of the host device. A weight coefficient obtained through the learning is used as a weight coefficient of the neural network of the processing circuit. By inputting illuminance of external light to the processing circuit, set values of luminance and color tone selected by the users are calculated in the neural network of the processing circuit.

9. 发明申请

US20200312851A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20200312851A1
公开(公告)日：2020-10-01
申请号：US16898573
申请日：2020-06-11
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yasuhiko TAKEMURA , Yoshiyuki KUROKAWA
IPC分类号： H01L27/105 , H01L27/12 , H01L49/02 , H01L29/66 , H01L29/786 , G11C11/409 , G11C11/405 , H01L29/423 , G11C11/4094 , H01L27/108 , G11C11/56 , G11C11/401 , H01L29/49
摘要： A semiconductor device with a large storage capacity per unit area is provided. The disclosed semiconductor device includes a plurality of gain-cell memory cells each stacked over a substrate. Axes of channel length directions of write transistors of memory cells correspond to each other, and are substantially perpendicular to the top surface of the substrate. The semiconductor device can retain multi-level data. The channel of read transistors is columnar silicon (embedded in a hole penetrating gates of the read transistors). The channel of write transistors is columnar metal oxide (embedded in a hole penetrating the gates of the read transistors and gates, or write word lines, of the write transistors). The columnar silicon faces the gate of the read transistor with an insulating film therebetween. The columnar metal oxide faces the write word line with an insulating film, which is obtained by oxidizing the write word line, therebetween, and is electrically connected to the gate of the read transistor.

10. 发明申请

US20200028498A1 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 审中-公开
公开(公告)号：US20200028498A1
公开(公告)日：2020-01-23
申请号：US16511215
申请日：2019-07-15
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Hajime KIMURA , Yoshiyuki KUROKAWA
IPC分类号： H03K3/037 , G11C13/00 , G11C11/16 , G06N3/04
摘要： A semiconductor device capable of performing product-sum operation with low power consumption. The semiconductor device includes first and second logic circuits, first to fourth transistors, and first and second holding units. A low power supply potential input terminal of the first logic circuit is electrically connected to the first and third transistors. A low power supply potential input terminal of the second logic circuit is electrically connected to the second and fourth transistors. The potentials of second gates of the first and fourth transistors are held in the first holding unit as potentials corresponding to first data. The potentials of second gates of the second and third transistors are held in the second holding unit. The on/off states of the first to fourth transistors are determined by second data. A difference in signal input/output time between the first and second logic circuits depends on the first data and the second data.

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