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1. 发明授权

US11791810B2 Transposed delay line oscillator and method 有权
公开(公告)号：US11791810B2
公开(公告)日：2023-10-17
申请号：US17634590
申请日：2020-08-13
申请人： Nanowave Technologies Inc.
发明人： Charles William Tremlett Nicholls
IPC分类号： H03K5/1252 , H03D7/00 , H03K5/14 , H03D7/16 , H03D7/18 , H03B21/00 , H03B19/00 , H03B17/00
CPC分类号： H03K5/1252 , H03B19/00 , H03B21/00 , H03D7/00 , H03D7/161 , H03D7/18 , H03K5/14 , H03B17/00
摘要： A transposed delay line oscillator including a mode selection filter and a transposed delay line is provided. An output of the transposed delay line is coupled to an input of the mode selection filter to establish an oscillator loop. Based on the transposed delay line output, the mode selection filter generates a mode selection signal including an isolated oscillatory mode, in a Radio Frequency (RF) band. The transposed delay line receives the mode selection signal for transposition to an intermediate frequency of an intermediate frequency (IF) delay line. The IF delay line includes a delay filter and a phase noise suppression loop configured to suppress de-correlated transposition phase noise resulting from a delay of the delay filter. Suppression of phase noise in the IF delay line enables cancellation of transposition phase noise when transposing the IF delay line output to the RF band.

2. 发明授权

US09608597B2 Digital interpolator and method of interpolating 有权
公开(公告)号：US09608597B2
公开(公告)日：2017-03-28
申请号：US14788874
申请日：2015-07-01
申请人： The Swatch Group Research and Development Ltd.
发明人： Massimiliano Bracco
IPC分类号： H03B19/00 , H03H11/20 , H03H17/06 , H03L7/16 , H03H17/04 , H03B21/00
CPC分类号： H03H11/20 , H03B19/00 , H03B21/00 , H03H17/04 , H03H17/0444 , H03H17/06 , H03H17/0671 , H03L7/16
摘要： The present invention relates to a digital interpolator, comprising an input to receive an input signal at a first clock frequency and comprising an output to provide an interpolated signal at a second clock frequency larger than the first clock frequency. The interpolator comprises a differentiator connected to the input, an interpolator stage connected to a differentiator output, and an integrator connected to the output and connected to an output of the interpolator stage.

3. 发明授权

US09094022B2 Geographic locating remote endpoint monitor device, system, and methodology thereof 有权
标题翻译：地理定位远程端点监控设备，系统及其方法
公开(公告)号：US09094022B2
公开(公告)日：2015-07-28
申请号：US13740806
申请日：2013-01-14
申请人： Sensus Spectrum LLC
发明人： H. Britton Sanderford, Jr. , Robert E. Rouquette , Gary A. Naden , Marc L. Reed , Gordon J. Boudreaux , Michael R. Brown
IPC分类号： H03L7/08 , H04L5/06 , H04L5/16 , H04L25/06 , H04L25/49 , H04L27/12 , H04L27/233 , H04L27/32 , H04L27/34 , H04L27/36 , H04L27/38 , H03B21/00 , H04W36/08 , H04W72/04
CPC分类号： H03L7/08 , H03B21/00 , H04L5/06 , H04L5/16 , H04L25/061 , H04L25/4902 , H04L25/4921 , H04L27/12 , H04L27/2331 , H04L27/32 , H04L27/34 , H04L27/3433 , H04L27/3483 , H04L27/364 , H04L27/38 , H04L27/3845 , H04W36/08 , H04W72/0426
摘要： A cellular network includes a node configured to transmit a data packet on a predetermined frequency, first and second base stations configured to receive signals transmitted on the predetermined frequency, and a data concentrator. The first base station and the second base station are arranged in a cellular configuration such that a first coverage area of the first base station at least partially overlaps a second coverage area of the second base station. The first base station and the second base station each receive the data packet transmitted by the node. The data concentrator is configured to collect the data packet received by the first base station and the data packet received by the second base station. The data packet includes latitude and longitude data received from a global positioning system receiver such that a location of the node may be determined from a remote location.
摘要翻译：蜂窝网络包括被配置为在预定频率上发送数据分组的节点，被配置为接收以预定频率发送的信号的第一和第二基站以及数据集中器。第一基站和第二基站被布置成蜂窝配置，使得第一基站的第一覆盖区域至少部分地与第二基站的第二覆盖区域重叠。第一基站和第二基站各自接收节点发送的数据分组。数据集中器被配置为收集由第一基站接收的数据分组和由第二基站接收的数据分组。数据分组包括从全球定位系统接收机接收的纬度和经度数据，使得可以从远程位置确定节点的位置。

4. 发明授权

US09071195B2 Method and system for signal synthesis 有权
标题翻译：信号合成方法和系统
公开(公告)号：US09071195B2
公开(公告)日：2015-06-30
申请号：US13977804
申请日：2011-12-26
申请人： David Gabbay
发明人： David Gabbay
IPC分类号： H03B21/00 , G06F1/025
CPC分类号： H03B21/00 , G06F1/025
摘要： The invention describes methods and systems for digital synthesis of electric signals. According to the invention, one or more bit-patterns are provided, each indicative of a rectangular waveform having a characteristic frequency. Further to determining a selected signal frequency to be synthesized, a selected bit-pattern associated therewith is obtained. Bits of the selected bit-pattern are cyclically serialized to generate a substantially rectangular waveform signal comprising the characteristic frequency. Then, the signal is filtered to suppress spurious frequencies outside a certain unfiltered frequency band which corresponds to the selected bit-pattern to thereby obtain a filtered signal with prominent frequency component corresponding to the selected signal frequency.
摘要翻译：本发明描述了用于数字合成电信号的方法和系统。根据本发明，提供了一个或多个位模式，每个位图形指示具有特征频率的矩形波形。为了确定要合成的所选择的信号频率，获得与其相关联的所选择的位模式。所选位图案的位被循环地串行化以产生包括特征频率的基本上矩形的波形信号。然后，对信号进行滤波，以抑制对应于所选位模式的某个未滤波频带之外的杂散频率，从而获得具有对应于所选信号频率的突出频率分量的滤波信号。

5. 发明授权

US09065458B2 Frequency synthesis and noise reduction 有权
标题翻译：频率合成和降噪
公开(公告)号：US09065458B2
公开(公告)日：2015-06-23
申请号：US13641333
申请日：2011-04-11
申请人： Robert John Mark Longstone , Ian Morrison Graham
发明人： Robert John Mark Longstone , Ian Morrison Graham
IPC分类号： H03B21/00 , H03L7/22 , H03B19/00 , H03B21/02 , H03B21/04 , H03B21/01
CPC分类号： H03L7/22 , H03B19/00 , H03B21/00 , H03B21/01 , H03B21/02 , H03B21/025 , H03B21/04
摘要： A frequency synthesizer and oscillator are disclosed for reducing noise in processed signals. The synthesizer and oscillator comprise an array of frequency dividers adapted to receive an input signal, which is derived from a single signal source having a prescribed frequency. The synthesizer and oscillator further comprise at least one frequency multiplier coupled to at least one of the frequency dividers, such that in use, the dividers and the at least one multiplier are operable to generate a plurality of frequencies which are coherent with the prescribed frequency. A regulated power supply is also disclosed comprising a filter and first and second regulators, for reducing noise in the output voltage of the power supply.
摘要翻译：公开了一种用于降低处理信号中的噪声的频率合成器和振荡器。合成器和振荡器包括适于接收从具有规定频率的单个信号源导出的输入信号的分频器阵列。合成器和振荡器还包括耦合到至少一个分频器的至少一个频率乘法器，使得在使用中，分频器和至少一个乘法器可操作以产生与规定频率相干的多个频率。还公开了一种稳压电源，其包括滤波器和第一和第二调节器，用于降低电源的输出电压中的噪声。

6. 发明授权

US08719616B2 Method for encoder frequency-shift compensation 有权
标题翻译：编码器频移补偿方法
公开(公告)号：US08719616B2
公开(公告)日：2014-05-06
申请号：US13775098
申请日：2013-02-22
申请人： Seagate Technology, LLC
发明人： Koichi Wago , Sundeep Chauhan , David M. Tung
IPC分类号： G06F1/00 , H04L7/00
CPC分类号： H03L7/06 , H01J37/3174 , H03B21/00 , H03L7/08
摘要： A method for encoder frequency-shift compensation includes determining frequency values of an input encoder signal, determining repeatable frequency-shifts of the frequency values and generating a frequency-shift compensated clock using the repeatable frequency-shifts. A frequency-shift compensated clock includes a synthesizer configured to generate a frequency-shift compensated clock signal using repeatable frequency shifts and encoder clock signals.
摘要翻译：一种用于编码器频移补偿的方法包括：确定输入编码器信号的频率值，确定频率值的可重复频移，并使用可重复的频移产生频移补偿时钟。频移补偿时钟包括合成器，其被配置为使用可重复的频移和编码器时钟信号来产生频移补偿的时钟信号。

7. 发明申请

US20140028355A1 NOISE FILTERING FRACTIONAL-N FREQUENCY SYNTHESIZER AND OPERATING METHOD THEREOF 有权
标题翻译：噪声滤波分解频率合成器及其工作方法
公开(公告)号：US20140028355A1
公开(公告)日：2014-01-30
申请号：US13727948
申请日：2012-12-27
申请人： NATIONAL TAIWAN UNIVERSITY
发明人： SHEN-IUAN LIU , KUN-HSUN LIAO
IPC分类号： H03B21/00
CPC分类号： H03B21/00 , H03L7/081 , H03L7/0814 , H03L7/1976 , H03L7/23
摘要： The present invention discloses a noise filtering fractional-n frequency synthesizer and an operating method thereof. The noise filtering fractional-n frequency synthesizer comprises a filter, a frequency calibration loop, a phase calibration loop and a digitally controlled delay line. The filter receives a first frequency division signal and generates a filtered signal. The frequency calibration loop is coupled to the filter and generates a first control signal. The phase calibration loop is coupled to the filter and the frequency calibration loop, and generates a second control signal. The digitally controlled delay line is coupled to the phase calibration loop and receives the second control signal. Thus, quantization noise of the fractional-n frequency synthesizer can be reduced, and phase noise of the fractional-n frequency synthesizer can be improved. In addition, the system remains locked after the filter outputs the signal.
摘要翻译：本发明公开了一种噪声滤波分数n频率合成器及其操作方法。噪声滤波分数n频率合成器包括滤波器，频率校准回路，相位校准回路和数字控制延迟线。滤波器接收第一分频信号并产生滤波信号。频率校准环耦合到滤波器并产生第一控制信号。相位校准环路耦合到滤波器和频率校准环路，并产生第二控制信号。数字控制的延迟线耦合到相位校准回路并接收第二控制信号。因此，可以减小分数n频率合成器的量化噪声，并且可以提高分数n频率合成器的相位噪声。另外，滤波器输出信号后，系统保持锁定状态。

8. 发明授权

US08633735B2 Signal level adjusting device and high-frequency apparatus 有权
标题翻译：信号电平调节装置和高频装置
公开(公告)号：US08633735B2
公开(公告)日：2014-01-21
申请号：US13200024
申请日：2011-09-15
申请人： Yasuo Kitayama , Hiroyuki Demura , Naoki Onishi
发明人： Yasuo Kitayama , Hiroyuki Demura , Naoki Onishi
IPC分类号： H03B21/00
CPC分类号： H03B21/00 , H03G1/0058 , H03G3/30 , H03L5/00
摘要： To provide, in a frequency synthesizer including: a variable attenuator provided at a subsequent stage of a voltage controlled oscillator; a detector; and a control unit outputting a control voltage for adjusting an attenuation amount of the variable attenuator via a digital/analog converter in accordance with a detection voltage, a technology with which a spurious due to a change in an output of the digital/analog converter can be suppressed. A low-pass filter is provided between an output side of a digital/analog converter and a variable attenuator to cut a frequency component corresponding to an overshoot generated when an output of the digital/analog converter is changed. Further, a period of time from when a control unit outputs a control voltage to when it reads a signal level detected by a detector is set to a period of time longer than a time constant of the low-pass filter determined by a cut-off frequency of the low-pass filter so that no influence is exerted on an operation of automatically controlling the signal level.
摘要翻译：提供一种频率合成器，包括：设置在压控振荡器的后续级的可变衰减器; 检测器以及控制单元，其根据检测电压输出用于经由数字/模拟转换器调整可变衰减器的衰减量的控制电压，由于数字/模拟转换器的输出的变化引起的寄生的杂散技术被压制在数字/模拟转换器的输出侧和可变衰减器之间提供低通滤波器，以便在数字/模拟转换器的输出改变时产生的过冲相应的剪切频率分量。此外，从控制单元输出控制电压到读取检测器检测到的信号电平的时间段被设置为比由截止器确定的低通滤波器的时间常数更长的时间段低通滤波器的频率，从而不会对自动控制信号电平的操作产生影响。

9. 发明授权

US08575973B1 Frequency synthesizer with zero deterministic jitter 有权
标题翻译：具有零确定性抖动的频率合成器
公开(公告)号：US08575973B1
公开(公告)日：2013-11-05
申请号：US13481038
申请日：2012-05-25
申请人： Xianyao Wang , Peter E. Sheldon , Christopher M. Green
发明人： Xianyao Wang , Peter E. Sheldon , Christopher M. Green
IPC分类号： H03B21/00
CPC分类号： H03B21/00 , G06F1/022 , H03B2202/02
摘要： A frequency synthesizer system may generate two intermediate clock signals, each intermediate clock signal having the same nominal frequency (fN), the same cycle pattern with deterministic jitter, and the same corresponding average frequency (fA). However, the cycle pattern in one intermediate clock signal may be a specified number (N) of cycles out of phase with respect to the cycle pattern in the other intermediate clock signal. The cycle pattern may recur every 2N cycles in each intermediate clock signal. The duration of each cycle in each of the two intermediate clock signals is defined by fN and the deterministic jitter in the cycle pattern. An output clock signal may be generated by phase interpolating by two (2) the two intermediate clock signals, and dividing the resulting phase interpolated clock signal by N. The resulting output clock signal has an accurate frequency commensurate with fA/N, and is free of deterministic jitter.
摘要翻译：频率合成器系统可以产生两个中间时钟信号，每个中间时钟信号具有相同的标称频率（fN），具有确定性抖动的相同周期模式和相同的相应平均频率（fA）。然而，一个中间时钟信号中的周期模式可以是相对于另一个中间时钟信号中的周期模式的异相的指定数量（N）个周期。在每个中间时钟信号中，循环模式可以每2N个循环重复。两个中间时钟信号中每一个周期的持续时间由fN和循环模式中的确定性抖动来定义。可以通过两（2）个中间时钟信号进行相位内插来产生输出时钟信号，并将得到的相位内插时钟信号除以N.由此产生的输出时钟信号具有与fA / N相当的精确频率，并且是空闲的的确定性抖动。

10. 发明申请

US20130154690A1 NESTED DIGITAL DELTA-SIGMA MODULATOR 有权
标题翻译：数字数字三角形调制器
公开(公告)号：US20130154690A1
公开(公告)日：2013-06-20
申请号：US13715529
申请日：2012-12-14
申请人： University College Cork -National University of Ireland, Cork
发明人： Michael Peter Kennedy
IPC分类号： H03B21/00
CPC分类号： H03B21/00 , H03L7/1974
摘要： Methods and systems are disclosed that provide a radio frequency synthesizer that generates precise frequencies over a large radio frequency range. The radio frequency synthesizer can provide a high resolution of frequency generation and still provide precise frequencies over a range of radio frequencies. The precision and resolution while maintaining a large operating range come from the ability of the frequency synthesizer to generate frequencies as a product of a plurality of moduli. For example, the frequency can be generated from a reference frequency using a first modulus and a second modulus. The plurality of modulo can be implemented using nested digital delta-sigma modulators in a fractional-N frequency synthesizer.
摘要翻译：公开了提供在大的射频范围内产生精确频率的射频合成器的方法和系统。无线电频率合成器可以提供高分辨率的频率产生，并且还能在无线电频率范围内提供精确的频率。维持较大工作范围的精度和分辨率来自于频率合成器产生频率作为多个模数乘积的能力。例如，可以使用第一模数和第二模数从参考频率产生频率。可以使用分数N频率合成器中的嵌套数字Δ-Σ调制器来实现多个模数。

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