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51. 发明授权

US06879201B1 Glitchless pulse generator 有权
标题翻译：无毛刺脉冲发生器
公开(公告)号：US06879201B1
公开(公告)日：2005-04-12
申请号：US10114524
申请日：2002-04-01
申请人： Siuki Chan
发明人： Siuki Chan
IPC分类号： G06F7/68 , H03K3/00 , H03K5/00 , H03K5/04
CPC分类号： G06F7/68 , H03K5/04 , H03K2005/00247
摘要： A glitchless T length pulse is generated by coupling a trigger signal and the latched output of a counter. The trigger signal initiates the start of the T length pulse, and the latched output of the counter initiates the end of the T length pulse after counting up a duration of T from a number of clock cycles of a clock signal. Latching the output of the counter prior to terminating the T length pulse eliminates glitches. Accuracy of the count determining the length of the T length pulse may be increased by latching the trigger signal with the clock signal to generated a synchronized trigger signal, and using the synchronized trigger signal to initiate the T length pulse.
摘要翻译：通过将触发信号和计数器的锁存输出相耦合来产生无毛刺T长度脉冲。触发信号启动T长度脉冲的开始，并且计数器的锁存输出在从时钟信号的时钟周期的多个时钟周期中向上计数持续时间T之后启动T长度脉冲的结束。在终止T长度脉冲之前对计数器的输出进行锁存可消除毛刺。确定T长度脉冲长度的计数的精度可以通过用触发信号锁存触发信号来产生同步的触发信号并使用同步触发信号来启动T长度脉冲来增加。

52. 发明申请

US20030085742A1 Clocking and synchronization circuitry 有权
公开(公告)号：US20030085742A1
公开(公告)日：2003-05-08
申请号：US10116601
申请日：2002-04-04
申请人： Infineon Technologies Aktiengesellschaft
发明人： Raj Kumar Jain
IPC分类号： H03K019/00 , H03L007/06
CPC分类号： H03L7/06 , H03K2005/00247
摘要： A clocking and synchronization circuitry is disclosed. A plurality of windows is provided to accommodate jitters in a clock with respect to a reference clock. A plurality of delayed state cycles is generated from the clock signal for clocking internal operations within the clocked integrated circuit.

53. 发明授权

US06271696B1 Phase adjustment circuit 失效
标题翻译：相位调整电路
公开(公告)号：US06271696B1
公开(公告)日：2001-08-07
申请号：US09440155
申请日：1999-11-15
申请人： Naoki Kobayashi
发明人： Naoki Kobayashi
IPC分类号： H03K513
CPC分类号： H03L7/0805 , G06F1/10 , H03K5/131 , H03K5/133 , H03K2005/00104 , H03K2005/00247 , H03L7/0814
摘要： A phase adjustment circuit of the present invention includes a plurality of input terminals which input a plurality of clock signals, respectively, and a plurality of first elements which input the clock signals, respectively, and adjust the clock signals, respectively. The phase adjustment circuit has a second element which compares the phase of a reference clock signal and the phase of an output signal from one of the first elements and outputs a compared result. A third element inputs the compared result and controls each of the first elements based on the compared result. Another phase adjustment circuit of the present invention includes a plurality of input terminals, which input a plurality of clock signals, respectively; a plurality of first elements, which input the clock signals, respectively, and oscillates the clock signals, respectively; and a second element which compares the phase of a reference clock signal and the phase of an output signal from one of the first elements and outputs a compared result. The first elements input the compared result and oscillate the clock signals, respectively, based on the compared result. A method of the present invention for adjusting the phase between a plurality of clock signals includes delaying each of the clock signals by a delay amount; comparing the phase of a reference clock signal and the phase of one of the delayed clock signals which is delayed during the delaying step; and controlling the delay amount based on the compared result which is compared during the comparing step.
摘要翻译：本发明的相位调整电路包括分别输入多个时钟信号的多个输入端子和分别输入时钟信号的多个第一元件，并分别调整时钟信号。相位调整电路具有第二元件，其将参考时钟信号的相位与来自第一元件之一的输出信号的相位进行比较，并输出比较结果。第三个元素输入比较结果，并根据比较结果控制每个第一个元素。本发明的另一个相位调整电路包括分别输入多个时钟信号的多个输入端子; 分别输入时钟信号并振荡时钟信号的多个第一元件; 以及第二元件，其比较参考时钟信号的相位和来自所述第一元件之一的输出信号的相位，并输出比较结果。第一个元素输入比较结果，并根据比较结果分别振荡时钟信号。用于调整多个时钟信号之间的相位的本发明的方法包括延迟每个时钟信号延迟量; 比较参考时钟信号的相位和在延迟步骤期间延迟的延迟时钟信号之一的相位; 以及基于在比较步骤期间比较的比较结果来控制延迟量。

54. 发明授权

US5987010A System and method for providing FDD and TDD modes of operation for a wireless communications device 失效
标题翻译：为无线通信设备提供FDD和TDD操作模式的系统和方法
公开(公告)号：US5987010A
公开(公告)日：1999-11-16
申请号：US856541
申请日：1997-05-15
申请人： Paul G. Schnizlein
发明人： Paul G. Schnizlein
IPC分类号： H04B7/26 , H04J3/00
CPC分类号： H04J3/0685 , H03K2005/00247
摘要： A system and method is described herein for providing FDD and TDD modes of operation for a wireless communications device. The system includes a clock signal for FDD mode operation, a separate clock signal for TDD mode operation, where the TDD mode clock is twice the frequency of the FDD clock. Additionally, a counter is provided for counting bit times during a transmission or receive frame. The clock counter is reloaded after a pre-specified count is achieved. The pre-specified count is twice as great in TDD mode operation than in FDD mode operation to account for the fact that the bit periods are twice as long in FDD operation than during TDD operation since transmit and receive are at different frequencies and are not sharing the same channel.
摘要翻译：本文描述了一种用于为无线通信设备提供FDD和TDD操作模式的系统和方法。该系统包括用于FDD模式操作的时钟信号，用于TDD模式操作的单独时钟信号，其中TDD模式时钟是FDD时钟频率的两倍。此外，还提供了一个计数器，用于在发送或接收帧期间计数位时间。在实现预先指定的计数之后重新加载时钟计数器。在FDD模式操作中，预先指定的计数是在FDD模式操作中的两倍，以解决在FDD操作中比TDD操作中的位周期长两倍的事实，因为发送和接收处于不同的频率并且不共享同一频道

55. 发明授权

US5107264A Digital frequency multiplication and data serialization circuits 失效
标题翻译：数字频率乘法和数据串行电路
公开(公告)号：US5107264A
公开(公告)日：1992-04-21
申请号：US588254
申请日：1990-09-26
申请人： Ilva I. Novof
发明人： Ilva I. Novof
IPC分类号： H03K5/00 , H03M9/00 , H04J3/04
CPC分类号： H03M9/00 , H03K5/00006 , H04J3/047 , H03K2005/00234 , H03K2005/00247 , H03K2005/00286
摘要： A digital clock frequency multiplication and data serialization circuit for converting Q parallel data bits into a serial data stream is provided. A clock phase generator is coupled to receive the clock signal of the Q parallel data bits and output in response thereto Q synchronous clocks each of different phase. Logic circuitry is coupled to simultaneously receive the Q synchronous clocks and the Q parallel data bits. The Q synchronous clocks are used by the logic to gate a respective one of the Q parallel data bits such that the Q parallel data bits are sequentially output therefrom as a serial data stream. Circuits are provided for simultaneous frequency multiplication and return-to-zero data serialization and simultaneous frequency multiplication and nonreturn-to-zero data serialization. Further, digital clock frequency multiplication and synchronization circuits for converting a low frequency signal to a high frequency signal are described.

56. 发明授权

US5073733A Delay circuit with muting to prevent noise due to random data at output 失效
标题翻译：延迟电路，以防止随机数据在输出噪声
公开(公告)号：US5073733A
公开(公告)日：1991-12-17
申请号：US510702
申请日：1990-04-18
申请人： Masaya Tanno , Masato Onaya
发明人： Masaya Tanno , Masato Onaya
IPC分类号： H03H17/08 , H03H17/00 , H03K5/00 , H03K5/135
CPC分类号： H03K5/135 , H03K2005/00247 , H03K2005/0026 , H03K2005/00267 , H03K2005/00273
摘要： A delay circuit includes a memory addresses of which is designated by a counter incremented in response to each clock signal from an initial value set by an initial value setting circuit to an end value. A digital signal is written into an address as designated and read and converted into an analog signal to be outputted at an output terminal through a buffer amplifier. A delay time is determined by the writing timing and the reading timing of the digital signal. If the delay time is to be varied in the course of a delaying operation, a further initial value is set in the counter. A control signal for returning the counter in the initial value is generated by a first signal generating circuit when the end value is reached and a setting completion signal is generated by a second signal generating circuit when a setting of the further initial value is completed, and in response to both the signals, a muting signal is generated by a muting signal generating circuit, whereby the buffer amplifier mutes the output signal in response to the muting signal to prevent a noise due to random data from occurring at the output terminal.

57. 发明授权

US4745310A Programmable delay circuit 失效
标题翻译：可编程延迟电路
公开(公告)号：US4745310A
公开(公告)日：1988-05-17
申请号：US125755
申请日：1987-11-23
申请人： Mavin C. Swapp
发明人： Mavin C. Swapp
IPC分类号： H03K5/00 , H03K5/13 , H03K5/159
CPC分类号： H03K5/131 , H03K2005/00247 , H03K2005/00273
摘要： A monolithically integrated delay circuit is provided that comprises a gate coupled for receiving a digital input signal. The output of the gate is capacitively loaded whereby the output signal has a sloping downward transition. A line receiver has a first input coupled to said gate and a second input coupled for receiving an analog signal for comparing the analog signal with the output of the gate and for providing a digital output signal that is delayed with respect to the digital input signal.
摘要翻译：提供了一种单片集成的延迟电路，其包括耦合用于接收数字输入信号的栅极。栅极的输出电容负载，从而输出信号具有向下倾斜的转变。线路接收机具有耦合到所述门的第一输入和耦合用于接收模拟信号的第二输入，用于将模拟信号与门的输出进行比较，并提供相对于数字输入信号延迟的数字输出信号。

58. 发明授权

US4737670A Delay control circuit 失效
标题翻译：延时控制电路
公开(公告)号：US4737670A
公开(公告)日：1988-04-12
申请号：US670454
申请日：1984-11-09
申请人： Steven S. Chan
发明人： Steven S. Chan
IPC分类号： G06F1/10 , H03K5/00 , H03K5/13 , H03K19/003 , H03K19/0175 , H03K19/173
CPC分类号： H03K19/00323 , H03K5/131 , H03K2005/00097 , H03K2005/00247
摘要： A circuit (40) constructed in accordance with this invention includes a ring oscillator (25) to provide a signal which is dependent on the propagation delays of the inverters (33, 34, 35) comprising the ring oscillator, therefore the frequency of the ring oscillator is inversely dependent upon the propagation delays of the inverter comprising the ring oscillator. Means (37) are provided to determine the propagation delay introduced by the components in the ring oscillator by measuring the frequency of the output signal produced by the ring oscillator which provides a signal to a multiplexer (36) which selects among a number of preset delay components (26) those components which are necessary to ensure that the propagation delay caused by the circuitry (not shown) connected to the input lead (21) of the circuit constructed in accordance with this invention plus the propagation delay introduced by the selectable delay elements is nearly a constant propagation delay.
摘要翻译：根据本发明构造的电路（40）包括环形振荡器（25），用于提供取决于包括环形振荡器的反相器（33,34,35）的传播延迟的信号，因此环的频率振荡器与包括环形振荡器的反相器的传播延迟成反比。提供装置（37）以通过测量由环形振荡器产生的输出信号的频率来确定由环形振荡器中的组件引入的传播延迟，该环形振荡器向多路复用器（36）提供信号，多路复用器选择多个预设延迟组件（26）为确保由连接到根据本发明构造的电路的输入引线（21）的电路（未示出）引起的传播延迟加上由可选延迟元件引入的传播延迟所必需的那些部件几乎是恒定的传播延迟。

59. 发明授权

US4675546A Edge programmable timing signal generator 失效
标题翻译：边缘可编程定时信号发生器
公开(公告)号：US4675546A
公开(公告)日：1987-06-23
申请号：US893033
申请日：1986-08-04
申请人： John R. Shaw
发明人： John R. Shaw
IPC分类号： H03K5/04 , H03K5/13 , H03K3/017
CPC分类号： H03K5/04 , H03K5/131 , H03K2005/00058 , H03K2005/00247 , H03K2005/0026
摘要： An inexpensive edge programmable timing signal generator for generating timing signals having complete edge programmability for accommodating incrementally adjustable variable pulse widths. The timing circuit is particularly useful in memory testing devices, where generation of a multiplicity of clock phases is required. A delay register delays an input timing signal generated by a coarse timing circuit by a predetermined amount of time, and a pair of rising and falling edge delay lines receive and delay the input and delayed timing signals by further predetermined amounts of time. The signals output from the rising and falling edge delay lines are applied to an OR gate, the output of which is applied to an EXCLUSIVE OR gate for selectively inverting the signal output from the OR gate. The circuit is inexpensive and takes up very little circuit board area.
摘要翻译：一种便宜的边缘可编程定时信号发生器，用于产生具有完整边缘可编程性的定时信号，以适应增量可调的可变脉冲宽度。定时电路在需要生成多个时钟相位的存储器测试装置中特别有用。延迟寄存器将由粗定时电路产生的输入定时信号延迟预定的时间量，并且一对上升沿和下降沿延迟线接收并延迟输入和延迟的定时信号进一步预定的时间量。从上升沿和下降沿延迟线输出的信号被施加到或门，其输出被施加到异或门以选择性地反相从或门输出的信号。电路价格便宜，电路板面积很小。

60. 发明授权

US4635256A Formatter for high speed test system 失效
标题翻译：格式化高速测试系统
公开(公告)号：US4635256A
公开(公告)日：1987-01-06
申请号：US611446
申请日：1984-05-17
申请人： Richard F. Herlein
发明人： Richard F. Herlein
IPC分类号： G01R31/317 , G01R31/319 , G01R31/3193 , H03K5/00 , H03K5/13 , H03K5/14 , G01R31/28
CPC分类号： H03K5/131 , G01R31/31713 , G01R31/3191 , G01R31/31922 , G01R31/31928 , G01R31/31935 , G01R31/31937 , H03K5/14 , G01R31/31926 , H03K2005/00247 , H03K2005/00254 , H03K2005/0026
摘要： A formatting circuit for a high speed integrated circuit test system controls the application of timed data pulses to the input terminals of the device being tested, generates strobe signals to control comparators connected to the output terminals of the device being tested, and provides circuitry to decode error signals received from the device being tested. The formatting circuit routes all critical signal paths to the device under test over separate signal lines, thereby allowing compensation for the different propagation delay of each signal path. The input transitions and output strobe signals for the device being tested are not fixed in time with respect to the system clock, but are referenced to it. This enables drive data cycles and compare data cycles to be less dependent on the system clock, and permits them to overlap and cross test period boundaries. Multiple test vectors for a given test period are permitted and error correlator decodes error signals produced by incorrect output signals from the device under test. The error correlator decodes these error signals and logs them in a memory location corresponding to the proper test vector.
摘要翻译：用于高速集成电路测试系统的格式化电路控制定时数据脉冲到被测设备的输入端的应用，产生选通信号以控制连接到正被测试设备的输出端的比较器，并提供解码电路从正在测试的设备接收的错误信号。格式化电路通过单独的信号线将所有关键信号路径路由到被测设备，从而允许补偿每个信号路径的不同传播延迟。正在测试的设备的输入转换和输出选通信号在系统时钟上并不是及时固定的，而是参考它。这使得驱动数据周期和比较数据周期不太依赖于系统时钟，并允许它们重叠并交叉测试周期边界。允许给定测试周期的多个测试向量，并且误差相关器解码来自被测器件的错误输出信号产生的误差信号。误差相关器对这些误差信号进行解码并将其记录在与正确的测试向量相对应的存储器位置。

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