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51. 发明授权

US06731513B2 Shielded multi-conductor interconnect bus for MEMS 有权
标题翻译：用于MEMS的屏蔽多导体互连总线
公开(公告)号：US06731513B2
公开(公告)日：2004-05-04
申请号：US10099724
申请日：2002-03-15
申请人： Murray Steven Rodgers , Stephen Matthew Barnes
发明人： Murray Steven Rodgers , Stephen Matthew Barnes
IPC分类号： H05K702
CPC分类号： B81B7/0006 , G02B26/0841 , H01L23/147 , H01L23/49872 , H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A shielded multi-conductor interconnect bus for use in interconnecting MEM devices with control signal sources or the like and a method of fabricating a shielded multi-conductor interconnect bus are disclosed. In one embodiment, a shielded interconnect bus formed on a substrate (20) includes a plurality of electrically conductive lines (42) arranged in sets of one, two or more conductive lines between electrically conductive shield walls (46, 66). The electrically conductive lines (42) are surrounded by layers of dielectric material (30, 50). An electrically conductive shield (78) overlies the electrically conductive lines (42) and electrically conductive shield walls (46, 66).
摘要翻译：公开了一种用于将MEM器件与控制信号源等互连的屏蔽多导体互连总线以及制造屏蔽多导体互连总线的方法。在一个实施例中，形成在衬底（20）上的屏蔽互连总线包括在导电屏蔽壁（46,66）之间布置成一组，两根或多根导电线的多个导电线（42）。导电线（42）被介电材料层（30,50）包围。导电屏蔽（78）覆盖在导电线（42）和导电屏蔽壁（46,66）之间。

52. 发明授权

US06670634B2 Silicon carbide interconnect for semiconductor components 失效
标题翻译：用于半导体元件的碳化硅互连
公开(公告)号：US06670634B2
公开(公告)日：2003-12-30
申请号：US10351742
申请日：2003-01-27
申请人： Salman Akram , Alan G. Wood
发明人： Salman Akram , Alan G. Wood
IPC分类号： H01L2358
CPC分类号： G01R1/06711 , G01R1/07314 , H01L23/13 , H01L23/498 , H01L23/49872 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： An interconnect for semiconductor components includes a substrate, and interconnect contacts on the substrate for electrically engaging component contacts on the components. The interconnect contacts include silicon carbide conductive layers, and conductors in electrical communication with the silicon carbide conductive layers. The silicon carbide conductive layers provides a wear resistant surface, and improved heat transfer between the component contacts and the interconnect contacts. The silicon carbide conductive layers can comprise doped silicon carbide, or alternately thermally oxidized silicon carbide. The interconnect can be configured for use with a testing apparatus for testing discrete components such as dice or chip scale packages, or alternately for use with a testing apparatus for testing wafer sized components, such as wafers, panels and boards. In addition, the interconnect can be configured for constructing semiconductor packages and electronic assemblies such as multi chip modules.
摘要翻译：用于半导体部件的互连件包括衬底和衬底上的互连触点，用于电连接部件上的组件触点。互连触点包括碳化硅导电层和与碳化硅导电层电连通的导体。碳化硅导电层提供耐磨表面，并且改善部件触点和互连触点之间的热传递。碳化硅导电层可以包括掺杂的碳化硅，或交替地热氧化的碳化硅。互连可以被配置用于与用于测试分立元件（例如骰子或芯片尺寸封装）的测试设备一起使用，或者替代地与用于测试晶片尺寸的元件（例如晶片，面板和板）的测试设备一起使用。此外，互连可以被配置用于构造半导体封装和诸如多芯片模块的电子组件。

53. 发明申请

US20030173654A1 Shielded multi-conductor interconnect bus for MEMS 有权
标题翻译：用于MEMS的屏蔽多导体互连总线
公开(公告)号：US20030173654A1
公开(公告)日：2003-09-18
申请号：US10099724
申请日：2002-03-15
发明人： Murray Steven Rodgers , Stephen Matthew Barnes
IPC分类号： H01L023/552
CPC分类号： B81B7/0006 , G02B26/0841 , H01L23/147 , H01L23/49872 , H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A shielded multi-conductor interconnect bus for use in interconnecting MEM devices with control signal sources or the like and a method of fabricating a shielded multi-conductor interconnect bus are disclosed. In one embodiment, a shielded interconnect bus formed on a substrate (20) includes a plurality of electrically conductive lines (42) arranged in sets of one, two or more conductive lines between electrically conductive shield walls (46, 66). The electrically conductive lines (42) are surrounded by layers of dielectric material (30, 50). An electrically conductive shield (78) overlies the electrically conductive lines (42) and electrically conductive shield walls (46, 66).
摘要翻译：公开了一种用于将MEM器件与控制信号源等互连的屏蔽多导体互连总线以及制造屏蔽多导体互连总线的方法。在一个实施例中，形成在衬底（20）上的屏蔽互连总线包括在导电屏蔽壁（46,66）之间布置成一组，两根或多根导电线的多个导电线（42）。导电线（42）被介电材料层（30,50）包围。导电屏蔽（78）覆盖在导电线（42）和导电屏蔽壁（46,66）之间。

54. 发明授权

US6002578A Ceramic substrate, circuit substrate and electronic circuit substrate by use thereof and method for preparing ceramic substrate 失效
标题翻译：陶瓷基板，电路基板及其电子电路基板及其制造方法
公开(公告)号：US6002578A
公开(公告)日：1999-12-14
申请号：US698688
申请日：1996-09-04
申请人： Motoo Kumagai , Keiichi Kato
发明人： Motoo Kumagai , Keiichi Kato
IPC分类号： H01L23/498 , H05K1/00 , H01G4/06 , C04B35/46
CPC分类号： H01L23/49894 , H01L23/49872 , H01L2924/0002 , H05K1/0298 , H05K2201/0187
摘要： A ceramic substrate comprises having two or more functional portions separated from each other, by providing a first region comprising a first dielectric porcelain having an insulating layer at the crystal grain boundaries of a semiconductor porcelain containing a semiconductivizing agent and a second region comprising a second dielectric porcelain with different dielectric constant from the first dielectric porcelain through the difference in amount or kind of the semiconductivizing agent from the first region.
摘要翻译：陶瓷基板包括具有两个或更多个功能部分，通过提供第一区域，该第一区域包括在包含半导体化剂的半导体瓷器的晶界处具有绝缘层的第一电介质陶瓷和包含第二电介质的第二区域通过来自第一区域的半导体剂的量或种类的差异，与第一介电瓷的介电常数不同的瓷器。

55. 发明申请

US20190131265A1 CHIP PACKAGE ASSEMBLY WITH ENHANCED INTERCONNECTS AND METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20190131265A1
公开(公告)日：2019-05-02
申请号：US15798748
申请日：2017-10-31
申请人： Xilinx, Inc.
发明人： Jaspreet Singh Gandhi
IPC分类号： H01L23/00 , H01L23/498 , H01L21/48
CPC分类号： H01L24/16 , H01L21/4853 , H01L23/49816 , H01L23/49872 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/81 , H01L2224/03001 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05073 , H01L2224/0508 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05573 , H01L2224/05583 , H01L2224/05647 , H01L2224/05666 , H01L2224/10145 , H01L2224/10175 , H01L2224/11001 , H01L2224/1145 , H01L2224/1146 , H01L2224/1182 , H01L2224/13017 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13565 , H01L2224/1357 , H01L2224/13647 , H01L2224/13686 , H01L2224/16057 , H01L2224/16227 , H01L2224/16238 , H01L2224/81002 , H01L2224/81193 , H01L2224/8121 , H01L2224/8123 , H01L2224/81815 , H01L2924/0561 , H01L2924/14 , H01L2924/3841 , H01L2924/01074 , H01L2924/01023 , H01L2924/00014 , H01L2924/01047 , H01L2924/014 , H01L2924/00012
摘要： An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate. The first contact pad is disposed on the first substrate and coupled to the first circuitry. The first pillar electrically disposed over the first contact pad. The first pillar protection layer is hydrophobic to solder and is disposed on a side surface of the first pillar.

56. 发明授权

US10003028B2 Hybrid carbon-metal interconnect structures 有权
公开(公告)号：US10003028B2
公开(公告)日：2018-06-19
申请号：US15614306
申请日：2017-06-05
申请人： INTEL CORPORATION
发明人： Hans-Joachim Barth
IPC分类号： H01L29/06 , H01L51/00 , H01L23/532 , H01L21/768 , H01L23/14 , H01L21/48 , H01L23/522 , H01L23/64 , H01L23/00 , H01L29/16 , H01L23/498
CPC分类号： H01L51/0048 , H01L21/4853 , H01L21/486 , H01L21/768 , H01L21/76805 , H01L21/76849 , H01L21/76852 , H01L21/76879 , H01L23/147 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49872 , H01L23/5226 , H01L23/5227 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/53276 , H01L23/645 , H01L24/13 , H01L24/16 , H01L24/48 , H01L29/1606 , H01L2221/1094 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/451 , H01L2224/48227 , H01L2924/12032 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/15311 , H01L2924/014 , H01L2924/00
摘要： Embodiments of the present disclosure are directed towards techniques and configurations for hybrid carbon-metal interconnect structures in integrated circuit assemblies. In one embodiment, an apparatus includes a substrate, a metal interconnect layer disposed on the substrate and configured to serve as a growth initiation layer for a graphene layer and the graphene layer, wherein the graphene layer is formed directly on the metal interconnect layer, the metal interconnect layer and the graphene layer being configured to route electrical signals. Other embodiments may be described and/or claimed.

57. 发明申请

US20180047589A1 LEAD CARRIER WITH PRINT FORMED PACKAGE COMPONENTS AND CONDUCTIVE PATH REDISTRIBUTION STRUCTURES 审中-公开
公开(公告)号：US20180047589A1
公开(公告)日：2018-02-15
申请号：US15542075
申请日：2016-05-04
申请人： Philip E ROGREN , EOPLEX LIMITED
发明人： Philip E ROGREN
IPC分类号： H01L21/48 , H01L23/495 , H01L23/498 , H01L21/56
CPC分类号： H01L21/4832 , H01L21/568 , H01L23/3107 , H01L23/49541 , H01L23/49548 , H01L23/49861 , H01L23/49872 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/85207 , H01L2924/00014 , H01L2924/181 , H01L2924/18301 , H01L2924/00012 , H01L2224/05599
摘要： A lead carrier includes a temporary support layer, member, medium, or carrier upon which are dispersed a plurality of package sites, organized in a predetermined pattern such as a matrix or array. Each package site within a continuous sheet of mold compound of the lead carrier includes a semiconductor die; a set of terminal structures, each having a top side and an opposing back side that is exposed at a back side of the continuous sheet of mold compound; and a set of electrical current path redistribution structures, each formed as an elongate wiring structure having a first end, a second end distinct from the first end, a top surface, an opposing bottom surface, a width, and a thickness between its top and bottom surfaces. Each redistribution structure as-fabricated is either electrically pre-coupled to a predetermined terminal structure, or electrically isolated from each terminal structure.

58. 发明授权

US09343363B2 Through-silicon vias and interposers formed by metal-catalyzed wet etching 有权
标题翻译：通过金属催化湿法蚀刻形成的硅通孔和插入层
公开(公告)号：US09343363B2
公开(公告)日：2016-05-17
申请号：US14213046
申请日：2014-03-14
申请人： Semprius, Inc.
发明人： Matthew Meitl , Christopher Bower
IPC分类号： H01L21/302 , H01L21/768 , H01L23/498 , H01L23/14 , H01L21/306 , H01L21/308
CPC分类号： H01L21/76898 , H01L21/30604 , H01L21/3081 , H01L23/147 , H01L23/49827 , H01L23/49838 , H01L23/49872 , H01L2924/0002 , H01L2924/00
摘要： Provided are methods for making a through-silicon via feature in a silicon substrate and related systems, such as by forming a noble metal structure on a silicon substrate support surface to generate silicon substrate contact regions that are in contact with or proximate to the noble metal structure; exposing at least a portion of the silicon substrate support surface and noble metal structure to an etchant to preferentially etch the silicon substrate contact regions compared to silicon substrate non-contact regions until the etch front reaches the silicon substrate bottom surface.
摘要翻译：提供了在硅衬底和相关系统中制造硅硅通孔特征的方法，例如通过在硅衬底支撑表面上形成贵金属结构以产生与贵金属接触或接近贵金属的硅衬底接触区域结构体; 将硅衬底支撑表面和贵金属结构的至少一部分暴露于蚀刻剂，以与硅衬底非接触区域相比优先蚀刻硅衬底接触区域，直到蚀刻前沿到达硅衬底底表面。

59. 发明授权

US09318498B2 Buried hard mask for embedded semiconductor device patterning 有权
标题翻译：嵌入式硬掩模用于嵌入式半导体器件图案化
公开(公告)号：US09318498B2
公开(公告)日：2016-04-19
申请号：US13735156
申请日：2013-01-07
申请人： Cypress Semiconductor Corporation
发明人： Scott A. Bell , Angela Tai Hui , Simon S. Chan
IPC分类号： H01L21/3205 , H01L27/115 , H01L21/8238 , H01L21/3213
CPC分类号： H01L27/11521 , H01L21/32139 , H01L21/823828 , H01L21/823857 , H01L23/49811 , H01L23/49844 , H01L23/49872 , H01L23/49894 , H01L27/11546
摘要： Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device can be manufactured by forming a core region of the semiconductor device and forming a periphery region of the semiconductor device. A first polysilicon region can then be formed over the core and periphery regions of the semiconductor device. A first mask is formed on the first poly silicon layer and a second polysilicon layer is disposed such that the second polysilicon layer covers the first mask. A second mask can then be formed on the second polysilicon layer. After forming the second mask, portions of the first and second polysilicon layers that are uncovered by either the first or second masks are removed.
摘要翻译：对半导体装置的制造方法和装置以及这样的半导体装置进行说明。根据本公开的各个方面，可以通过形成半导体器件的芯区域并形成半导体器件的外围区域来制造半导体器件。然后可以在半导体器件的芯部和外围区域上形成第一多晶硅区域。第一掩模形成在第一多晶硅层上，并且第二多晶硅层被布置成使得第二多晶硅层覆盖第一掩模。然后可以在第二多晶硅层上形成第二掩模。在形成第二掩模之后，去除由第一或第二掩模未覆盖的第一和第二多晶硅层的部分。

60. 发明申请

US20150279756A1 THROUGH SUBSTRATE VIAS AND DEVICE 有权
标题翻译：通过基板VIAS和设备
公开(公告)号：US20150279756A1
公开(公告)日：2015-10-01
申请号：US14440084
申请日：2013-10-31
申请人： SILEX MICROSYSTEMS AB
发明人： Ulf Erlesand , Edvard Kälvesten
IPC分类号： H01L23/15 , C25D5/02 , H01L21/768 , H01L23/498 , B81B7/00
CPC分类号： H01L23/15 , B81B7/007 , B81C1/00095 , C25D5/02 , H01L21/50 , H01L21/76879 , H01L23/49827 , H01L23/49872 , H01L2924/0002 , H01L2924/00
摘要： Method of making through-substrate-vias in glass substrates includes providing a first substrate on which a plurality of needles protruding vertically from the substrate are made; providing a second substrate made of glass; locating the substrates adjacent each other such that the needles on the first substrate face the second substrate; applying heat to a temperature where the glass softens, by heating the glass or the needle substrate or both; applying a force such that the needles on the first substrate penetrate into the glass to provide impressions in the glass; and finally, removing the first substrate and providing material filling the impressions in the second substrate made of glass. A device includes a silicon substrate having a cavity in which a MEMS component is accommodated, and a cap wafer made of a material having a low dielectric constant, and through substrate vias of metal, is bonded to the silicon substrate.
摘要翻译：在玻璃基板中制造贯通基板通孔的方法包括提供第一基板，其上形成有从基板垂直突出的多个针; 提供由玻璃制成的第二衬底; 将基板相邻地定位，使得第一基板上的针朝向第二基板; 通过加热玻璃或针基材或两者，将热量施加到玻璃软化的温度; 施加力，使得第一基底上的针穿透玻璃以在玻璃中产生印模; 最后，移除第一基片并提供填充由玻璃制成的第二基片的印模的材料。一种器件包括具有其中容纳MEMS部件的空腔的硅基板和由具有低介电常数的材料制成的盖晶片，并且通过金属的基板通孔接合到硅基板。

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